From patchwork Wed Oct 2 08:00:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 11170603 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B36251709 for ; Wed, 2 Oct 2019 08:01:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 921E2222C0 for ; Wed, 2 Oct 2019 08:01:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="MWuN0Z7j" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727350AbfJBIBT (ORCPT ); Wed, 2 Oct 2019 04:01:19 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17307 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727270AbfJBIBS (ORCPT ); Wed, 2 Oct 2019 04:01:18 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 02 Oct 2019 01:01:16 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 02 Oct 2019 01:01:16 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 02 Oct 2019 01:01:16 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 2 Oct 2019 08:01:16 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 2 Oct 2019 08:01:15 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 2 Oct 2019 08:01:15 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.102]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 02 Oct 2019 01:01:15 -0700 From: JC Kuo To: , , CC: , , , , , , JC Kuo Subject: [PATCH 4/6] dt-bindings: phy: tegra: Add Tegra194 support Date: Wed, 2 Oct 2019 16:00:49 +0800 Message-ID: <20191002080051.11142-5-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191002080051.11142-1-jckuo@nvidia.com> References: <20191002080051.11142-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1570003276; bh=xIRa56stX3owbUbxdta+NzKWZ/tN6XIJqm8j5g4nv0M=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=MWuN0Z7jup13PxpDOzGbwAkHJnu9K5ZvPBoeh1mo7NbmApLd4qblcruD2Ik7QYW0F aiyNs3JQR9kzP6jsRGlWeqwf6hRNBt7uR6t3gukWi6+GV57GMAkRamqAdyl/8L3Okx wDiNnnIkDPHTLXpjPJLXvNn3+i+yjSwMtpKRDaliF71rTXS9BrVgmFTjf2HQKDKG98 k1cfVUnHcWrZzhUrmyQ5jSwJ71Pl/WghL7fBrJEl8Vt/qK+8LLVWz4zwlvnwmV44i5 8DDMT12vvs4bJ4qEWz3YzShYQQn8wE2Yjd06XpRdPMqeqEk8lPb00JYtYQHHq6C07f kzfaTBY+/pNcA== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Extend the bindings to cover the set of features found in Tegra194. Note that, technically, there are four more supplies connected to the XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL) , but the power sequencing requirements of Tegra194 require these to be under the control of the PMIC. Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. To deal with this, a new device node property "nvidia,disable-gen2" was added to Tegra194 that be used to specifically disable Gen 2 speed for a particular USB 3.0 port so that the port can be limited to Gen 1 speed and avoid the instability. Signed-off-by: JC Kuo Acked-by: Thierry Reding --- .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 9fb682e47c29..3bef37e7c365 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -37,6 +37,7 @@ Required properties: - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" - Tegra186: "nvidia,tegra186-xusb-padctl" + - Tegra194: "nvidia,tegra194-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries: @@ -62,6 +63,10 @@ For Tegra186: - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. +For Tegra194: +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply + 3.3 V. +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. Pad nodes: ========== @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below: - sata: sata-0 - functions: "usb3-ss", "sata" +For Tegra194, the list of valid PHY nodes is given below: +- usb2: usb2-0, usb2-1, usb2-2, usb2-3 + - functions: "xusb" +- usb3: usb3-0, usb3-1, usb3-2, usb3-3 + - functions: "xusb" Port nodes: =========== @@ -221,6 +231,9 @@ Optional properties: is internal. In the absence of this property the port is considered to be external. +- nvidia,disable-gen2: A boolean property whose presence determines that a port + should be limited to USB 3.1 Gen 1. This properlty is only for Tegra194. + For Tegra124 and Tegra132, the XUSB pad controller exposes the following ports: - 3x USB2: usb2-0, usb2-1, usb2-2 @@ -233,6 +246,9 @@ For Tegra210, the XUSB pad controller exposes the following ports: - 2x HSIC: hsic-0, hsic-1 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 +For Tegra194, the XUSB pad controller exposes the following ports: +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 Examples: =========