From patchwork Wed Jan 15 14:13:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334923 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6A241398 for ; Wed, 15 Jan 2020 14:15:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8546724681 for ; Wed, 15 Jan 2020 14:15:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nEY82/y0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729708AbgAOONL (ORCPT ); Wed, 15 Jan 2020 09:13:11 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:40937 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729639AbgAOONK (ORCPT ); Wed, 15 Jan 2020 09:13:10 -0500 Received: by mail-wr1-f67.google.com with SMTP id c14so15889567wrn.7 for ; Wed, 15 Jan 2020 06:13:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PCdwe+dsjnxv3bml7N0qDZxbZ4I8SN1UrysTU8U3ets=; b=nEY82/y0BNZg4ZPeORMiuXFe/3DgtX+U5lo1ZtJ3hn5e08nKkdJbBqUlLNvOYjrZc+ 7ioEe0dTNAVDXPeWAR5n4202QgN6RV3Hct0i0HfCu1UGMI7f3VPvXyUbD2s6Z9E6L1U3 kAcoO6GbwWhQ+KhRrBmMiBtX03QSLSiigmXMOEBTfDuGovHeOB0z9sFdkzftXdN7S2k3 o/ESFR8PgVT5RBaDIVu8nFRcP9QafJAO6PUSV3ioLDTBqBX/Tc5qlhYxVXzpxtPTnV4M 8RMZyG7IKrBNEnPJC5vt4TOX7Eq4cNHgfCVbRqJNiLR8ZtV2KSqXAiIkAt+f/VV8kqs7 9oJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PCdwe+dsjnxv3bml7N0qDZxbZ4I8SN1UrysTU8U3ets=; b=Y7UMMj+ITGIIDGqYflH1TRtlHv0/W0LT+xWAMq5J6N0ud1sy3A1K8XvgjqgYyyPrN9 /B1qLgMigXVZ28bhV9AmqRA7PGJgyy/KVrRX1ZARIuvr6x/g2dao0yNfN25r+oMbQ6a2 08AiR3WHt7c1f/apof3oxtj7f6ftGVKmXn8Mc6Ufd7ZbHcy48lIrAnSLqmfzFYREg0uu FFaN+uUZLyKhne8zyY8aAOoP++pPSYPyrOz4DXtxP1jQhNXIYCwRps7hC27HYBpyqmeu l0vCKHqu1TXhQ09+A1/Ei2HhKgvYQBbOeJBDu0eg+CCj+5DZtY9Hz+Sjgz43n+XbW5Pp P87w== X-Gm-Message-State: APjAAAX85gqz1bsCkJoJ4vizh0ER3uUvfb1gMlKtXiybGsKDXcCx52J5 Rggma9qrgiy7YPw4wU44D5B7rQ== X-Google-Smtp-Source: APXvYqyFCs8W824zav4mO7iW6IJZ2oMXu8EgcO0ACxcSO5xMO78O+j9I88X7j/y/aOwE8yO8BrTnKw== X-Received: by 2002:adf:f484:: with SMTP id l4mr31381219wro.207.1579097587939; Wed, 15 Jan 2020 06:13:07 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:07 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Sriharsha Allenki , Anu Ramanathan , Shawn Guo , Andy Gross , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Jorge Ramirez-Ortiz , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 02/19] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Date: Wed, 15 Jan 2020 14:13:16 +0000 Message-Id: <20200115141333.1222676-3-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sriharsha Allenki Adds bindings for QCS404 USB PHY supporting Low-Speed, Full-Speed and Hi-Speed USB connectivity on Qualcomm chipsets. [bod: Converted to YAML. Changed name dropping snps component] Signed-off-by: Sriharsha Allenki Signed-off-by: Anu Ramanathan Signed-off-by: Bjorn Andersson Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Rob Herring Cc: Mark Rutland Cc: Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- .../bindings/phy/qcom,qcs404-usb-hs.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml new file mode 100644 index 000000000000..4bc7a3334b54 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qcs404-usb-hs.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys QCS-404 High-Speed PHY + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm QCS-404 Low-Speed, Full-Speed, Hi-Speed USB PHY + +properties: + compatible: + enum: + - qcom,qcs404-usb-hsphy + + reg: + maxItems: 1 + description: USB PHY base address and length of the register map. + + "#phy-cells": + const: 0 + description: Should be 0. See phy/phy-bindings.txt for details. + + clocks: + items: + - description: Rescource Power Management clock + - descirption: PHY AHB clock + - description: Retention clock + + clock-names: + items: + - const: ref + - const: phy + - const: sleep + + resets: + items: + - description: PHY core reset + - description: POR reset + + reset-names: + items: + - description: phy + - description: por + + vdd-supply: + maxItems: 1 + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + maxItems: 1 + description: phandle to the regulator 1.8V supply node. + + vdda3p3-supply: + maxItems: 1 + description: phandle to the regulator 3.3V supply node. + +Example: + + phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x7a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + };