| Message ID | 20200210120723.91794-5-bryan.odonoghue@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable Qualcomm QCS 404 HS/SS USB | expand |
On Mon, Feb 10, 2020 at 12:07:09PM +0000, Bryan O'Donoghue wrote: > From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> > > Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY > appears in a number of SoCs on various flavors of 20nm and 28nm nodes. > > Based on Sriharsha Allenki's <sallenki@codeaurora.org> original > definitions. > > [bod: converted to yaml format] > > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> > Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- > .../devicetree/bindings/phy/qcom,usb-ss.yaml | 83 +++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml > new file mode 100644 > index 000000000000..377b9e1e39d3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY > + > +maintainers: > + - Bryan O'Donoghue <bryan.odonoghue@linaro.org> > + > +description: | > + Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY > + > +properties: > + compatible: > + enum: > + - qcom,usb-ssphy Pretty generic... Only 1 SS USB PHY in all of QCom forever? IOW, this needs an SoC specific compatible. > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 > + > + clocks: > + items: > + - description: rpmcc clock > + - description: PHY AHB clock > + - description: SuperSpeed pipe clock > + > + clock-names: > + items: > + - const: ref > + - const: ahb > + - const: pipe > + > + vdd-supply: > + description: phandle to the regulator VDD supply node. > + > + vdda1p8-supply: > + description: phandle to the regulator 1.8V supply node. > + > + resets: > + items: > + - description: COM reset > + - description: PHY reset line > + > + reset-names: > + items: > + - const: com > + - const: phy > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - clock-names > + - vdd-supply > + - vdda1p8-supply > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-qcs404.h> > + #include <dt-bindings/clock/qcom,rpmcc.h> > + usb3_phy: usb3-phy@78000 { > + compatible = "qcom,usb-ssphy"; > + reg = <0x78000 0x400>; > + #phy-cells = <0>; > + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, > + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, > + <&gcc GCC_USB3_PHY_PIPE_CLK>; > + clock-names = "ref", "ahb", "pipe"; > + resets = <&gcc GCC_USB3_PHY_BCR>, > + <&gcc GCC_USB3PHY_PHY_BCR>; > + reset-names = "com", "phy"; > + vdd-supply = <&vreg_l3_1p05>; > + vdda1p8-supply = <&vreg_l5_1p8>; > + }; > +... > -- > 2.25.0 >
On 18/02/2020 20:45, Rob Herring wrote: >> + - qcom,usb-ssphy > Pretty generic... Only 1 SS USB PHY in all of QCom forever? > > IOW, this needs an SoC specific compatible. > Analog IP doesn't generally move across different litho nodes without tweaks. I take your point. I'll take another look at the naming convention here.
diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml new file mode 100644 index 000000000000..377b9e1e39d3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +maintainers: + - Bryan O'Donoghue <bryan.odonoghue@linaro.org> + +description: | + Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +properties: + compatible: + enum: + - qcom,usb-ssphy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: rpmcc clock + - description: PHY AHB clock + - description: SuperSpeed pipe clock + + clock-names: + items: + - const: ref + - const: ahb + - const: pipe + + vdd-supply: + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + description: phandle to the regulator 1.8V supply node. + + resets: + items: + - description: COM reset + - description: PHY reset line + + reset-names: + items: + - const: com + - const: phy + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda1p8-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcs404.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + usb3_phy: usb3-phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "ahb", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + }; +...