From patchwork Thu Mar 26 13:45:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11460067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 244621668 for ; Thu, 26 Mar 2020 13:45:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F0EDC20787 for ; Thu, 26 Mar 2020 13:45:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="oXf3ZOxT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727885AbgCZNp0 (ORCPT ); Thu, 26 Mar 2020 09:45:26 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:42537 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727847AbgCZNpY (ORCPT ); Thu, 26 Mar 2020 09:45:24 -0400 Received: by mail-wr1-f65.google.com with SMTP id h15so7833068wrx.9 for ; Thu, 26 Mar 2020 06:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XFHG5+N/s7f8jdUDEuCLFX/hWvMN/ArmpVpj0Lv1sZA=; b=oXf3ZOxT4u0zMm5X8QXKxA/Q0qhLbk+gSoUGuuMLTzLUfeSUrEFeACmZINOcW2EEXU CKrD6SLol01NFTX/JeEUGG35dddkPw/Wzpj2pLlqi+YrG5keEtTyam9smIlrcwVT8scQ UfjfA167zZQLtnuyRkTCJfRhnlydB5flGx4Pk4unP28Zac6qi9uEcaRkbSXJ0D8ri9Vx 5xmp1Z61F2D2jQuz7sCET3QqvIXPneZuVcdetl1+m7+oYaGtTrnu358/FURXTiM6IMHI Z1rchVCAB8I5rlZdI2J7rB8p1YCTCrLQPuYRVvB7JRAyXoBLFKeBw3LVfbQ6OqCLxdnX FXVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XFHG5+N/s7f8jdUDEuCLFX/hWvMN/ArmpVpj0Lv1sZA=; b=GvNz09Qb72lVURLA/4Fq6PGhgwx4UJ8Liya82Fc3yZWhbl5I48xwlNuwHu4Tyv/aBJ m/W35qZl69PLbTOEQne1mEZWw64AKw6z3WuvFxFsOKnIgs2MJZrTc7MvBmhybeAgOLvc GKmJ5vL5Bh0S5qAEJexlGun4c+p50gcQBbRBmywrF2Pyj1oUixOIXR4uXo6U4bZVcdtb tkj2PIYS2iYDzjvprVrVYaVE/xbxVsJdOdeCfudST1q4S/dwwwmqHFYVW2yikVi1Lq6J Ao6sEdC2bapCGhlUHL9vvhZD49BzvL63Wf5AM/YuqOmoO80Tn+tJ52MM6D1wZAfOnEJi j+1w== X-Gm-Message-State: ANhLgQ2URMSYfLiqAnrSIf9UpjOrWTGE1dndJ7Alp8v+zJE6TZjTJugA 52IMsDJHPy6PvALTWytQIAxA9w== X-Google-Smtp-Source: ADFU+vu7yb/02zWifja9JlrE8hb/mJzudE0Zpo/fJUGlHmyIkrsZlmbUV8smuqOCGgaGjd6t28l6cg== X-Received: by 2002:adf:b35d:: with SMTP id k29mr9627002wrd.239.1585230321357; Thu, 26 Mar 2020 06:45:21 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:5c5f:613e:f775:b6a2]) by smtp.gmail.com with ESMTPSA id h29sm4079617wrc.64.2020.03.26.06.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2020 06:45:20 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/14] usb: dwc3: meson-g12a: support the GXL/GXM DWC3 host phy disconnect Date: Thu, 26 Mar 2020 14:45:00 +0100 Message-Id: <20200326134507.4808-9-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org On the Amlogic GXL/GXM SoCs, the OTG PHY status signals are always connected to the DWC3 controller, thus crashing the controller when switching to OTG mode when port is not populated with a device/cable to Host. Amlogic added a bit to disconnect the OTG PHY status signals from the DWC3 to be used when switching the OTG PHY as Device to the DWC2 controller. The drawback is that it makes the DWC3 port state machine stall and needs a full reset of the DWC3 controller to get connect status to the port connected to the OTG PHY, but not the other one. Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 43b398b7b1f7..f3f247d38606 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -131,6 +131,7 @@ struct dwc3_meson_g12a; struct dwc3_meson_g12a_drvdata { bool otg_switch_supported; + bool otg_phy_host_port_disable; struct clk_bulk_data *clks; int num_clks; const char **phy_names; @@ -155,6 +156,19 @@ static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv); +/* + * For GXL and GXM SoCs: + * USB Phy muxing between the DWC2 Device controller and the DWC3 Host + * controller is buggy when switching from Device to Host when USB port + * is unpopulated, it causes the DWC3 to hard crash. + * When populated (including OTG switching with ID pin), the switch works + * like a charm like on the G12A platforms. + * In order to still switch from Host to Device on an USB Type-A port, + * an U2_PORT_DISABLE bit has been added to disconnect the DWC3 Host + * controller from the port, but when used the DWC3 controller must be + * reset to recover usage of the port. + */ + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, @@ -290,6 +304,13 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv, enum phy_mode mode) { if (mode == PHY_MODE_USB_DEVICE) { + if (priv->otg_mode != USB_DR_MODE_OTG && + priv->drvdata->otg_phy_host_port_disable) + /* Isolate the OTG PHY port from the Host Controller */ + regmap_update_bits(priv->usb_glue_regmap, USB_R1, + USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, + FIELD_PREP(USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, + BIT(USB2_OTG_PHY))); regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, USB_R0_U2D_ACT); regmap_update_bits(priv->usb_glue_regmap, USB_R0, @@ -297,6 +318,12 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv, regmap_update_bits(priv->usb_glue_regmap, USB_R4, USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0); } else { + if (priv->otg_mode != USB_DR_MODE_OTG && + priv->drvdata->otg_phy_host_port_disable) { + regmap_update_bits(priv->usb_glue_regmap, USB_R1, + USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0); + msleep(500); + } regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, 0); regmap_update_bits(priv->usb_glue_regmap, USB_R4, @@ -429,6 +456,13 @@ static int dwc3_meson_g12a_role_set(struct device *dev, enum usb_role role) if (mode == priv->otg_phy_mode) return 0; + if (priv->drvdata->otg_phy_host_port_disable) + dev_warn_once(priv->dev, "Manual OTG switch is broken on this "\ + "SoC, when manual switching from "\ + "Host to device, DWC3 controller "\ + "will need to be resetted in order "\ + "to recover usage of the Host port"); + return dwc3_meson_g12a_otg_mode_set(priv, mode); }