From patchwork Mon Jun 8 19:26:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Saenz Julienne X-Patchwork-Id: 11593907 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78ACD739 for ; Mon, 8 Jun 2020 19:28:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 689B42076A for ; Mon, 8 Jun 2020 19:28:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726703AbgFHT2S (ORCPT ); Mon, 8 Jun 2020 15:28:18 -0400 Received: from mx2.suse.de ([195.135.220.15]:39674 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726410AbgFHT1g (ORCPT ); Mon, 8 Jun 2020 15:27:36 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 43A70AEBF; Mon, 8 Jun 2020 19:27:38 +0000 (UTC) From: Nicolas Saenz Julienne To: f.fainelli@gmail.com, gregkh@linuxfoundation.org, wahrenst@gmx.net, robh@kernel.org, mathias.nyman@linux.intel.com, Eric Anholt , bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-usb@vger.kernel.org, Rob Herring , Nicolas Saenz Julienne Cc: linux-kernel@vger.kernel.org, tim.gover@raspberrypi.org, helgaas@kernel.org, lorenzo.pieralisi@arm.com Subject: [PATCH 4/9] ARM: dts: bcm2711: Add reset controller to xHCI node Date: Mon, 8 Jun 2020 21:26:56 +0200 Message-Id: <20200608192701.18355-5-nsaenzjulienne@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200608192701.18355-1-nsaenzjulienne@suse.de> References: <20200608192701.18355-1-nsaenzjulienne@suse.de> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The chip is hardwired to the board's PCIe bus and needs to be properly setup trough a firmware routine after a PCI fundamental reset. Pass the reset controller phandle that takes care of triggering the initialization to the relevant PCI device. Signed-off-by: Nicolas Saenz Julienne --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 47e7c9c14ddf..2646c858449f 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -207,6 +207,13 @@ phy1: ethernet-phy@1 { }; }; +&pcie0 { + usb@1,0 { + reg = <0 0 0 0 0>; + resets = <&usb_reset>; + }; +}; + /* uart0 communicates with the BT module */ &uart0 { pinctrl-names = "default";