Message ID | 20201010222351.7323-2-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | usb: dwc3: ulpi: Fix UPLI registers read/write ops | expand |
Hi, Serge Semin <Sergey.Semin@baikalelectronics.ru> writes: > In accordance with [1] the DWC_usb3 core sets the GUSB2PHYACCn.VStsDone > bit when the PHY vendor control access is done and clears it when the > application initiates a new transaction. The doc doesn't say anything > about the GUSB2PHYACCn.VStsBsy flag serving for the same purpose. Moreover > we've discovered that the VStsBsy flag can be cleared before the VStsDone > bit. So using the former as a signal of the PHY control registers > completion might be dangerous. Let's have the VStsDone flag utilized > instead then. > > [1] Synopsys DesignWare Cores SuperSpeed USB 3.0 xHCI Host Controller > Databook, 2.70a, December 2013, p.388 > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > --- > drivers/usb/dwc3/core.h | 1 + > drivers/usb/dwc3/ulpi.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index 2f04b3e42bf1..8d5e5bba1bc2 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -284,6 +284,7 @@ > > /* Global USB2 PHY Vendor Control Register */ > #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) > +#define DWC3_GUSB2PHYACC_DONE BIT(24) > #define DWC3_GUSB2PHYACC_BUSY BIT(23) > #define DWC3_GUSB2PHYACC_WRITE BIT(22) > #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) > diff --git a/drivers/usb/dwc3/ulpi.c b/drivers/usb/dwc3/ulpi.c > index e6e6176386a4..20f5d9aba317 100644 > --- a/drivers/usb/dwc3/ulpi.c > +++ b/drivers/usb/dwc3/ulpi.c > @@ -24,7 +24,7 @@ static int dwc3_ulpi_busyloop(struct dwc3 *dwc) > > while (count--) { > reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); > - if (!(reg & DWC3_GUSB2PHYACC_BUSY)) > + if (reg & DWC3_GUSB2PHYACC_DONE) are you sure this works in all supported versions of the core? John, could you confirm this for us? thanks
On Tue, Oct 27, 2020 at 11:15:24AM +0200, Felipe Balbi wrote: > > Hi, > > Serge Semin <Sergey.Semin@baikalelectronics.ru> writes: > > > In accordance with [1] the DWC_usb3 core sets the GUSB2PHYACCn.VStsDone > > bit when the PHY vendor control access is done and clears it when the > > application initiates a new transaction. The doc doesn't say anything > > about the GUSB2PHYACCn.VStsBsy flag serving for the same purpose. Moreover > > we've discovered that the VStsBsy flag can be cleared before the VStsDone > > bit. So using the former as a signal of the PHY control registers > > completion might be dangerous. Let's have the VStsDone flag utilized > > instead then. > > > > [1] Synopsys DesignWare Cores SuperSpeed USB 3.0 xHCI Host Controller > > Databook, 2.70a, December 2013, p.388 > > > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > --- > > drivers/usb/dwc3/core.h | 1 + > > drivers/usb/dwc3/ulpi.c | 2 +- > > 2 files changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > > index 2f04b3e42bf1..8d5e5bba1bc2 100644 > > --- a/drivers/usb/dwc3/core.h > > +++ b/drivers/usb/dwc3/core.h > > @@ -284,6 +284,7 @@ > > > > /* Global USB2 PHY Vendor Control Register */ > > #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) > > +#define DWC3_GUSB2PHYACC_DONE BIT(24) > > #define DWC3_GUSB2PHYACC_BUSY BIT(23) > > #define DWC3_GUSB2PHYACC_WRITE BIT(22) > > #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) > > diff --git a/drivers/usb/dwc3/ulpi.c b/drivers/usb/dwc3/ulpi.c > > index e6e6176386a4..20f5d9aba317 100644 > > --- a/drivers/usb/dwc3/ulpi.c > > +++ b/drivers/usb/dwc3/ulpi.c > > @@ -24,7 +24,7 @@ static int dwc3_ulpi_busyloop(struct dwc3 *dwc) > > > > while (count--) { > > reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); > > - if (!(reg & DWC3_GUSB2PHYACC_BUSY)) > > + if (reg & DWC3_GUSB2PHYACC_DONE) > > are you sure this works in all supported versions of the core? I can't be sure about that since I've got only the 2.70a version of the core. But as I said in the patch log it was a bit incorrect to use the BUSY flag here in the first place. So if there is no IP core peculiarity here which had been workarounded by polling the BUSY-flag, then I'd stick with the DONE-flag in the busy-loop. In the former case I'd suggest to add a useful comment why the BUSY-flag is required to be polled though... -Sergey > > John, could you confirm this for us? > > thanks > > -- > balbi
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 2f04b3e42bf1..8d5e5bba1bc2 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -284,6 +284,7 @@ /* Global USB2 PHY Vendor Control Register */ #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) +#define DWC3_GUSB2PHYACC_DONE BIT(24) #define DWC3_GUSB2PHYACC_BUSY BIT(23) #define DWC3_GUSB2PHYACC_WRITE BIT(22) #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) diff --git a/drivers/usb/dwc3/ulpi.c b/drivers/usb/dwc3/ulpi.c index e6e6176386a4..20f5d9aba317 100644 --- a/drivers/usb/dwc3/ulpi.c +++ b/drivers/usb/dwc3/ulpi.c @@ -24,7 +24,7 @@ static int dwc3_ulpi_busyloop(struct dwc3 *dwc) while (count--) { reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); - if (!(reg & DWC3_GUSB2PHYACC_BUSY)) + if (reg & DWC3_GUSB2PHYACC_DONE) return 0; cpu_relax(); }
In accordance with [1] the DWC_usb3 core sets the GUSB2PHYACCn.VStsDone bit when the PHY vendor control access is done and clears it when the application initiates a new transaction. The doc doesn't say anything about the GUSB2PHYACCn.VStsBsy flag serving for the same purpose. Moreover we've discovered that the VStsBsy flag can be cleared before the VStsDone bit. So using the former as a signal of the PHY control registers completion might be dangerous. Let's have the VStsDone flag utilized instead then. [1] Synopsys DesignWare Cores SuperSpeed USB 3.0 xHCI Host Controller Databook, 2.70a, December 2013, p.388 Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/usb/dwc3/core.h | 1 + drivers/usb/dwc3/ulpi.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)