From patchwork Wed Feb 3 10:26:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 12063933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F969C433E9 for ; Wed, 3 Feb 2021 10:28:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE39264E38 for ; Wed, 3 Feb 2021 10:28:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233863AbhBCK1w (ORCPT ); Wed, 3 Feb 2021 05:27:52 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:36954 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233694AbhBCK1f (ORCPT ); Wed, 3 Feb 2021 05:27:35 -0500 X-UUID: 109044f3a5c24026a4f5930e4b0eaccf-20210203 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qJXyUkhTG3EiVikkkhafwsut5EHurgvUe+hMMeVXd64=; b=dnXVX1CYwJ4CMKrJYba4h/XDMwcANiwlJNop0YS7rA8ksPjSd55Yfm2RU5+Bw/82EJmsTGnOU8bnwRh3GBrzS0rOvzxdJ9iA8DTPuBGI8P7PP/cK62joq/xd1efg4pWLFzoNoLGesHCBDw9Sc0S136Lh17jGLgbpJ5D9/588zWo=; X-UUID: 109044f3a5c24026a4f5930e4b0eaccf-20210203 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 328501113; Wed, 03 Feb 2021 18:26:51 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 18:26:46 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 18:26:46 +0800 From: Chunfeng Yun To: Rob Herring , Matthias Brugger , Mathias Nyman CC: Greg Kroah-Hartman , , , , , , Ikjoon Jang , Nicolas Boichat , Chunfeng Yun Subject: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195 Date: Wed, 3 Feb 2021 18:26:41 +0800 Message-ID: <20210203102642.7353-2-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210203102642.7353-1-chunfeng.yun@mediatek.com> References: <20210203102642.7353-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 69C95C417298EC51AE23FB6CAB8FFF25126E6644A83787837E3078CAF3F85B592000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we should set the accurate interval according to 48Mhz for those controllers. Note: the first controller no need set it. Signed-off-by: Chunfeng Yun --- v2: fix typo of comaptible --- drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 8f321f39ab96..0a68c4ac8b48 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -68,11 +68,71 @@ #define SSC_IP_SLEEP_EN BIT(4) #define SSC_SPM_INT_EN BIT(1) +/* xHCI csr */ +#define LS_EOF 0x930 +#define LS_EOF_OFFSET 0x89 + +#define FS_EOF 0x934 +#define FS_EOF_OFFSET 0x2e + +#define SS_GEN1_EOF 0x93c +#define SS_GEN1_EOF_OFFSET 0x78 + +#define HFCNTR_CFG 0x944 +#define ITP_DELTA_CLK (0xa << 1) +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) +#define FRMCNT_LEV1_RANG (0x12b << 8) +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) + +#define SS_GEN2_EOF 0x990 +#define SS_GEN2_EOF_OFFSET 0x3c +#define EOF_OFFSET_MASK GENMASK(11, 0) + enum ssusb_uwk_vers { SSUSB_UWK_V1 = 1, SSUSB_UWK_V2, }; +/* + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval + * is calculated from the frame counter clock 24M, but in fact, the clock + * is 48M, so need change the interval. + */ +static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk) +{ + struct device *dev = mtk->dev; + struct usb_hcd *hcd = mtk->hcd; + u32 value; + + if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) + return; + + value = readl(hcd->regs + HFCNTR_CFG); + value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK); + value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG); + writel(value, hcd->regs + HFCNTR_CFG); + + value = readl(hcd->regs + LS_EOF); + value &= ~EOF_OFFSET_MASK; + value |= LS_EOF_OFFSET; + writel(value, hcd->regs + LS_EOF); + + value = readl(hcd->regs + FS_EOF); + value &= ~EOF_OFFSET_MASK; + value |= FS_EOF_OFFSET; + writel(value, hcd->regs + FS_EOF); + + value = readl(hcd->regs + SS_GEN1_EOF); + value &= ~EOF_OFFSET_MASK; + value |= SS_GEN1_EOF_OFFSET; + writel(value, hcd->regs + SS_GEN1_EOF); + + value = readl(hcd->regs + SS_GEN2_EOF); + value &= ~EOF_OFFSET_MASK; + value |= SS_GEN2_EOF_OFFSET; + writel(value, hcd->regs + SS_GEN2_EOF); +} + static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) { struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; @@ -407,6 +467,8 @@ static int xhci_mtk_setup(struct usb_hcd *hcd) ret = xhci_mtk_ssusb_config(mtk); if (ret) return ret; + + xhci_mtk_set_frame_interval(mtk); } ret = xhci_gen_setup(hcd, xhci_mtk_quirks); @@ -655,6 +717,7 @@ static const struct dev_pm_ops xhci_mtk_pm_ops = { #ifdef CONFIG_OF static const struct of_device_id mtk_xhci_of_match[] = { { .compatible = "mediatek,mt8173-xhci"}, + { .compatible = "mediatek,mt8195-xhci"}, { .compatible = "mediatek,mtk-xhci"}, { }, };