Message ID | 20220110201936.1371891-2-robert.hancock@calian.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show
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Mon, 10 Jan 2022 20:19:52 +0000 From: Robert Hancock <robert.hancock@calian.com> To: linux-usb@vger.kernel.org Cc: Thinh.Nguyen@synopsys.com, robh+dt@kernel.org, devicetree@vger.kernel.org, michal.simek@xilinx.com, balbi@kernel.org, gregkh@linuxfoundation.org, mounika.grace.akula@xilinx.com, manish.narani@xilinx.com, Robert Hancock <robert.hancock@calian.com> Subject: [PATCH v3 1/5] usb: dwc3: xilinx: Fix PIPE clock selection for USB2.0 mode Date: Mon, 10 Jan 2022 14:19:32 -0600 Message-Id: <20220110201936.1371891-2-robert.hancock@calian.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220110201936.1371891-1-robert.hancock@calian.com> References: <20220110201936.1371891-1-robert.hancock@calian.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MWHPR1201CA0002.namprd12.prod.outlook.com (2603:10b6:301:4a::12) To YT2PR01MB6270.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:4d::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ea1bee66-d9fe-4145-6d9b-08d9d4768f04 X-MS-TrafficTypeDiagnostic: YT3PR01MB6339:EE_ X-Microsoft-Antispam-PRVS: <YT3PR01MB63396700C7E6C45724FC2B8BEC509@YT3PR01MB6339.CANPRD01.PROD.OUTLOOK.COM> X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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Xilinx ZynqMP USB fixes
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expand
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diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c index 9cc3ad701a29..3bc035376394 100644 --- a/drivers/usb/dwc3/dwc3-xilinx.c +++ b/drivers/usb/dwc3/dwc3-xilinx.c @@ -167,8 +167,11 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data) /* Set PIPE Power Present signal in FPD Power Present Register*/ writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT); - /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ - writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); + /* Set the PIPE Clock Select bit in FPD PIPE Clock register if a USB3 + * PHY is in use, deselect otherwise + */ + writel(usb3_phy ? PIPE_CLK_SELECT : PIPE_CLK_DESELECT, + priv_data->regs + XLNX_USB_FPD_PIPE_CLK); ret = reset_control_deassert(crst); if (ret < 0) {
It appears that the PIPE clock should not be selected when only USB 2.0 is being used in the design and no USB 3.0 reference clock is used. Fix to set the correct value depending on whether a USB3 PHY is present. Fixes: 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms") Signed-off-by: Robert Hancock <robert.hancock@calian.com> --- drivers/usb/dwc3/dwc3-xilinx.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)