From patchwork Tue May 30 07:55:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Westerberg X-Patchwork-Id: 13259387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5996C77B7A for ; Tue, 30 May 2023 07:56:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229633AbjE3H4L (ORCPT ); Tue, 30 May 2023 03:56:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229623AbjE3H4K (ORCPT ); Tue, 30 May 2023 03:56:10 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8998FF1 for ; Tue, 30 May 2023 00:55:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685433353; x=1716969353; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=kZElLRbz5wDonx5jo805gHYCRvxa9gUzPWvxobbMozI=; b=UpIWbTwwc1mq+9XjQ0wraPCsZVE9/Vj9QRbUTTeVJqKENafz8N8aJp38 XrvT2nBLNDWRSCke4qe2ZdvMFOnMSI9/EdP62ZkruJLITthiDJNGvgEli wGvJ4WGJunWF4UqHmk+AVtbS3Jdokz12+aFrjDycjZEroycI4FdXimSKz U5Zhf76WA6xOXEndmS+ZnaMEPnbwNkairz5QknwYIMPCHae95k560RYOX phiDnQpX97bIb8IGXEbHeivrgGSayb+dCZpOzw+S9ZouN8GTsmtDwGH2O n3YPbP4/ZVbjb04SrCuy53Z7ToVpGyXfEQpUHERVQFW6gfUESgDEpDSzv Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="418329453" X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="418329453" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2023 00:55:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="683849260" X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="683849260" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga006.jf.intel.com with ESMTP; 30 May 2023 00:55:50 -0700 Received: by black.fi.intel.com (Postfix, from userid 1001) id B874253A; Tue, 30 May 2023 10:55:55 +0300 (EEST) From: Mika Westerberg To: linux-usb@vger.kernel.org Cc: Yehezkel Bernat , Michael Jamet , Lukas Wunner , Andreas Noever , beld zhang , Mario Limonciello , Bagas Sanjaya , Mika Westerberg Subject: [PATCH] thunderbolt: Mask ring interrupt on Intel hardware as well Date: Tue, 30 May 2023 10:55:55 +0300 Message-Id: <20230530075555.35239-1-mika.westerberg@linux.intel.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org When resuming from system sleep states the driver issues following warning on Intel hardware: thunderbolt 0000:07:00.0: interrupt for TX ring 0 is already enabled The reason for this is that the commit in question did not mask the ring interrupt on Intel hardware leaving the interrupt active. Fix this by masking it also in Intel hardware. Reported-by: beld zhang Closes: https://lore.kernel.org/linux-usb/ZHKW5NeabmfhgLbY@debian.me/ Fixes: c4af8e3fecd0 ("thunderbolt: Clear registers properly when auto clear isn't in use") Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello Signed-off-by: Mika Westerberg --- drivers/thunderbolt/nhi.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index 565892a2cdb9..a979f47109e3 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -56,9 +56,14 @@ static int ring_interrupt_index(const struct tb_ring *ring) static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring) { - if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) - return; - iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring); + if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) { + u32 val; + + val = ioread32(nhi->iobase + REG_RING_INTERRUPT_BASE + ring); + iowrite32(val & ~mask, nhi->iobase + REG_RING_INTERRUPT_BASE + ring); + } else { + iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring); + } } static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring)