| Message ID | 20231005102725.8458-1-piyush.mehta@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | usb: dwc3: core: disable 3.0 clock when operating in 2.0 device mode | expand |
On Thu, Oct 05, 2023 at 03:57:25PM +0530, Piyush Mehta wrote: > The GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK bit enable the feature of internal > 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock. This feature is > applicable when core is operating in 2.0 device mode. > > When this bit is set in host mode and core is in 2.0 device mode (maximum > speed = high-speed) then usb super speed devices not detected on host. > > To address the above issue added usb device mode conditional check. > > Fixes: 62b20e6e0dde ("usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode") > Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> > --- > DWC3 Register Map Link: > https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/GUCTL1-USB3_XHCI-Register > Register Name GUCTL1 > Bit: 26 > Bit Name: DEV_FORCE_20_CLK_FOR_30_CLK > --- > drivers/usb/dwc3/core.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 9c6bf054f15d..0cf1fe60628b 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -1202,6 +1202,7 @@ static int dwc3_core_init(struct dwc3 *dwc) > reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; > > if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && > + (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) && > (dwc->maximum_speed == USB_SPEED_HIGH || > dwc->maximum_speed == USB_SPEED_FULL)) > reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; > -- > 2.17.1 > > Hi, This is the friendly patch-bot of Greg Kroah-Hartman. You have sent him a patch that has triggered this response. He used to manually respond to these common problems, but in order to save his sanity (he kept writing the same thing over and over, yet to different people), I was created. Hopefully you will not take offence and will fix the problem in your patch and resubmit it so that it can be accepted into the Linux kernel tree. You are receiving this message because of the following common error(s) as indicated below: - You have marked a patch with a "Fixes:" tag for a commit that is in an older released kernel, yet you do not have a cc: stable line in the signed-off-by area at all, which means that the patch will not be applied to any older kernel releases. To properly fix this, please follow the documented rules in the Documetnation/process/stable-kernel-rules.rst file for how to resolve this. If you wish to discuss this problem further, or you have questions about how to resolve this issue, please feel free to respond to this email and Greg will reply once he has dug out from the pending patches received from other developers. thanks, greg k-h's patch email bot
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9c6bf054f15d..0cf1fe60628b 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1202,6 +1202,7 @@ static int dwc3_core_init(struct dwc3 *dwc) reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && + (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) && (dwc->maximum_speed == USB_SPEED_HIGH || dwc->maximum_speed == USB_SPEED_FULL)) reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
The GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK bit enable the feature of internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock. This feature is applicable when core is operating in 2.0 device mode. When this bit is set in host mode and core is in 2.0 device mode (maximum speed = high-speed) then usb super speed devices not detected on host. To address the above issue added usb device mode conditional check. Fixes: 62b20e6e0dde ("usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode") Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> --- DWC3 Register Map Link: https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/GUCTL1-USB3_XHCI-Register Register Name GUCTL1 Bit: 26 Bit Name: DEV_FORCE_20_CLK_FOR_30_CLK --- drivers/usb/dwc3/core.c | 1 + 1 file changed, 1 insertion(+)