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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002636A.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.26 via Frontend Transport; Tue, 12 Dec 2023 14:01:53 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 12 Dec 2023 08:01:19 -0600 From: Sanath S To: , , , , , , CC: Sanath S Subject: [PATCH 1/2] thunderbolt: Introduce tb_switch_reset_ports(), tb_port_reset() and usb4_port_reset() Date: Tue, 12 Dec 2023 19:30:46 +0530 Message-ID: <20231212140047.2021496-2-Sanath.S@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212140047.2021496-1-Sanath.S@amd.com> References: <20231212140047.2021496-1-Sanath.S@amd.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636A:EE_|SN7PR12MB7153:EE_ X-MS-Office365-Filtering-Correlation-Id: c3e2dd1f-9f39-43af-12a3-08dbfb1ae5fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2023 14:01:53.7743 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3e2dd1f-9f39-43af-12a3-08dbfb1ae5fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7153 Introduce the tb_switch_reset_ports() function that resets the downstream ports of a given switch. This helps us reset the USB4 links created by boot firmware during the init sequence. Introduce the tb_port_reset() helper function that resets the given port. Introduce the usb4_port_reset() function that performs the DPR of a given port. This function follows the CM guide specification 7.3 Suggested-by: Mario Limonciello Signed-off-by: Sanath S --- drivers/thunderbolt/switch.c | 31 ++++++++++++++++++++++++++++ drivers/thunderbolt/tb.h | 2 ++ drivers/thunderbolt/tb_regs.h | 1 + drivers/thunderbolt/usb4.c | 39 +++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index 44e9b09de47a..26ad6cc1ee91 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -626,6 +626,19 @@ int tb_port_unlock(struct tb_port *port) return 0; } +/** + * tb_port_reset() - Reset downstream port + * @port: Port to reset + * + * Helps to reconfigure the USB4 link by resetting the downstream port. + * + * Return: Returns 0 on success or an error code on failure. + */ +static int tb_port_reset(struct tb_port *port) +{ + return usb4_port_reset(port); +} + static int __tb_port_enable(struct tb_port *port, bool enable) { int ret; @@ -1547,6 +1560,24 @@ static void tb_dump_switch(const struct tb *tb, const struct tb_switch *sw) regs->__unknown1, regs->__unknown4); } +/** + * tb_switch_reset_ports() - Reset downstream ports of switch. + * @sw: Switch whose ports need to be reset. + * + * Return: Returns 0 on success or an error code on failure. + */ +int tb_switch_reset_ports(struct tb_switch *sw) +{ + struct tb_port *port; + int ret = -EINVAL; + + tb_switch_for_each_port(sw, port) { + if (tb_port_is_null(port) && port->cap_usb4) + ret = tb_port_reset(port); + } + return ret; +} + /** * tb_switch_reset() - reconfigure route, enable and send TB_CFG_PKG_RESET * @sw: Switch to reset diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h index e299e53473ae..f2687ec4ac53 100644 --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h @@ -797,6 +797,7 @@ void tb_switch_remove(struct tb_switch *sw); void tb_switch_suspend(struct tb_switch *sw, bool runtime); int tb_switch_resume(struct tb_switch *sw); int tb_switch_reset(struct tb_switch *sw); +int tb_switch_reset_ports(struct tb_switch *sw); int tb_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit, u32 value, int timeout_msec); void tb_sw_set_unplugged(struct tb_switch *sw); @@ -1281,6 +1282,7 @@ struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, int usb4_switch_add_ports(struct tb_switch *sw); void usb4_switch_remove_ports(struct tb_switch *sw); +int usb4_port_reset(struct tb_port *port); int usb4_port_unlock(struct tb_port *port); int usb4_port_hotplug_enable(struct tb_port *port); int usb4_port_configure(struct tb_port *port); diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h index 87e4795275fe..d49530bc0d53 100644 --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h @@ -389,6 +389,7 @@ struct tb_regs_port_header { #define PORT_CS_18_CSA BIT(22) #define PORT_CS_18_TIP BIT(24) #define PORT_CS_19 0x13 +#define PORT_CS_19_DPR BIT(0) #define PORT_CS_19_PC BIT(3) #define PORT_CS_19_PID BIT(4) #define PORT_CS_19_WOC BIT(16) diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c index 4277733d0021..55f7c163bf84 100644 --- a/drivers/thunderbolt/usb4.c +++ b/drivers/thunderbolt/usb4.c @@ -1073,6 +1073,45 @@ void usb4_switch_remove_ports(struct tb_switch *sw) } } +/** + * usb4_port_reset() - Reset USB4 downsteam port + * @port: USB4 port to reset. + * + * Helps to reconfigure USB4 link by resetting downstream port. + * + * Return: Returns 0 on success or an error code on failure. + */ +int usb4_port_reset(struct tb_port *port) +{ + int ret; + u32 val = 0; + + ret = tb_port_read(port, &val, TB_CFG_PORT, + port->cap_usb4 + PORT_CS_19, 1); + if (ret) + return ret; + + val = val | PORT_CS_19_DPR; + ret = tb_port_write(port, &val, TB_CFG_PORT, + port->cap_usb4 + PORT_CS_19, 1); + if (ret) + return ret; + + /* Wait for 10ms after requesting downstream port reset */ + msleep(10); + + ret = tb_port_read(port, &val, TB_CFG_PORT, + port->cap_usb4 + PORT_CS_19, 1); + if (ret) + return ret; + + val &= ~PORT_CS_19_DPR; + ret = tb_port_write(port, &val, TB_CFG_PORT, + port->cap_usb4 + PORT_CS_19, 1); + + return ret; +} + /** * usb4_port_unlock() - Unlock USB4 downstream port * @port: USB4 port to unlock