From patchwork Thu Apr 25 04:57:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashanth K X-Patchwork-Id: 13642866 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CB5C2C697; Thu, 25 Apr 2024 04:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714021097; cv=none; b=cAKMxfaZNRsqCD6Y3MFyVed40b3JtHG00jdLO/ppCQBXrdIQP6sRXUzk7cSSKnsJZ+tirkV+gKjfFVZRRP1hmNG+nhEtfvgfJyFuZVpAKmo9KgACmCCWTSCgu6n9l86tOj7EyIn9/6t7Fp1QKne9APj9HwS+7OJkDpFbDQNV/NE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714021097; c=relaxed/simple; bh=SXKhmE1mFSWFNXbTgKv60f+ty4UJ3XJhBfkQOjaM7fQ=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=A5JnywAvlsnzi+039vpBruMiPRNK5QKST/XwYtnAR183PmB/pIFdtXhuPYQanYmTYQLXWLtTO09uGHDDLGuYiyCOy1+hmW3BBTz4irHCc1SqrelYrxwRwFoZmuuZTp754nkrIfQhRiH6nr9JoZEBMNSpI8wRpdHIOApDAXll4s4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=jugf5Skt; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="jugf5Skt" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43P2jf4C021788; Thu, 25 Apr 2024 04:58:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=qcppdkim1; bh=C/eFcRc eePgjWKK1u/9J8UibNSm0qr+7zcLyo0PYzPg=; b=jugf5Skt3xw21Itn8lpJ7Q6 ZYnIqid5u9NKRLeCX/a38HITy/7V4nCTAIeKKXm/64FvKcrXZQv37HCHZg2tDgv/ wokohLHFcrFSBVwoweETzBDmfVTpOK12PuixjEsl0dscoRklmrt6rQc1ZHbFGf/F jTF5i2MRArZGb//EBc5MdzNkWHJ0eDT2KloG0SWEIcS5CWcUHSopCCa6j+lX3SX2 6/yAHKSlW58JaQdqB9AhX7/ajoPoFelK1FVkJyWli4CJbrvSsjzGgN2qrQYsMRHF GlYKHp/WbKEV1gd3XW4TSZ8qU5azePqu5Ez4Wj2EJGMOI8pDexzbD+34AHAoJDQ= = Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xqengg8uh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Apr 2024 04:58:12 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43P4wBgM011738 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Apr 2024 04:58:11 GMT Received: from hu-prashk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Apr 2024 21:58:08 -0700 From: Prashanth K To: Thinh Nguyen , Greg Kroah-Hartman CC: Wesley Cheng , , , Prashanth K , Subject: [PATCH v2] usb: dwc3: Wait unconditionally after issuing EndXfer command Date: Thu, 25 Apr 2024 10:27:49 +0530 Message-ID: <20240425045749.1493541-1-quic_prashk@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: YMF-tT2R4zSD9GAOEs30f2uw8t60rVhM X-Proofpoint-GUID: YMF-tT2R4zSD9GAOEs30f2uw8t60rVhM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-25_04,2024-04-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=871 priorityscore=1501 mlxscore=0 phishscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 clxscore=1011 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404250032 Currently all controller IP/revisions except DWC3_usb3 >= 310a wait 1ms unconditionally for ENDXFER completion when IOC is not set. This is because DWC_usb3 controller revisions >= 3.10a supports GUCTL2[14: Rst_actbitlater] bit which allows polling CMDACT bit to know whether ENDXFER command is completed. Consider a case where an IN request was queued, and parallelly soft_disconnect was called (due to ffs_epfile_release). This eventually calls stop_active_transfer with IOC cleared, hence send_gadget_ep_cmd() skips waiting for CMDACT cleared during EndXfer. For DWC3 controllers with revisions >= 310a, we don't forcefully wait for 1ms either, and we proceed by unmapping the requests. If ENDXFER didn't complete by this time, it leads to SMMU faults since the controller would still be accessing those requests. Fix this by ensuring ENDXFER completion by adding 1ms delay in __dwc3_stop_active_transfer() unconditionally. Cc: Fixes: b353eb6dc285 ("usb: dwc3: gadget: Skip waiting for CMDACT cleared during endxfer") Signed-off-by: Prashanth K Acked-by: Thinh Nguyen --- Changes in v2: Changed the patch logic from CMDACT polling to 1ms mdelay. Updated subject and commit accordingly. Link to v1: https://lore.kernel.org/all/20240422090539.3986723-1-quic_prashk@quicinc.com/ drivers/usb/dwc3/gadget.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 4df2661f6675..666eae94524f 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1724,8 +1724,7 @@ static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool int dep->resource_index = 0; if (!interrupt) { - if (!DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC3, 310A)) - mdelay(1); + mdelay(1); dep->flags &= ~DWC3_EP_TRANSFER_STARTED; } else if (!ret) { dep->flags |= DWC3_EP_END_TRANSFER_PENDING;