diff mbox series

[3/3] arm64: dts: imx8mq-evk: add typec node

Message ID 20240729081039.3904797-3-xu.yang_2@nxp.com (mailing list archive)
State Superseded
Headers show
Series [1/3] dt-bindings: usb: gpio-sbu-mux: Add an entry for PTN36043 | expand

Commit Message

Xu Yang July 29, 2024, 8:10 a.m. UTC 
The first port of USB with type-C connector, which has dual data
role and dual power role.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 93 ++++++++++++++++++++
 1 file changed, 93 insertions(+)

Comments

Dmitry Baryshkov July 29, 2024, 7:56 p.m. UTC | #1 
On Mon, Jul 29, 2024 at 04:10:39PM GMT, Xu Yang wrote:
> The first port of USB with type-C connector, which has dual data
> role and dual power role.
> 
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 93 ++++++++++++++++++++
>  1 file changed, 93 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index 7507548cdb16..008e8c37c76b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -6,6 +6,7 @@
>  
>  /dts-v1/;
>  
> +#include <dt-bindings/usb/pd.h>
>  #include "imx8mq.dtsi"
>  
>  / {
> @@ -27,6 +28,20 @@ pcie0_refclk: pcie0-refclk {
>  		clock-frequency = <100000000>;
>  	};
>  
> +	ptn36043: typec-mux {
> +		compatible = "nxp,ptn36043", "gpio-sbu-mux";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_typec_mux>;
> +		select-gpios =<&gpio3 15 GPIO_ACTIVE_LOW>;
> +		orientation-switch;
> +
> +		port {
> +			usb3_data_ss: endpoint {
> +				remote-endpoint = <&typec_con_ss>;
> +			};
> +		};

If this the "SBU" mux, then why is it connected to the SS lines?
Where are the SS lines further going?

> +	};
> +
>  	reg_pcie1: regulator-pcie {
>  		compatible = "regulator-fixed";
>  		pinctrl-names = "default";
> @@ -315,6 +330,50 @@ vgen6_reg: vgen6 {
>  			};
>  		};
>  	};
> +
> +	ptn5110: tcpc@50 {
> +		compatible = "nxp,ptn5110", "tcpci";
> +		reg = <0x50>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_typec>;
> +		interrupt-parent = <&gpio3>;
> +		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> +
> +		usb_con: connector {
> +			compatible = "usb-c-connector";
> +			label = "USB-C";
> +			power-role = "dual";
> +			data-role = "dual";
> +			try-power-role = "sink";
> +			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
> +			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
> +				     PDO_VAR(5000, 20000, 3000)>;
> +			op-sink-microwatt = <15000000>;
> +			self-powered;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +
> +					typec_dr_sw: endpoint {

the DR (dual role) isn't a physical signal. These ports descrbie HS
(high speed) lanes, please consider naming them correspondingly.

> +						remote-endpoint = <&usb3_drd_sw>;
> +					};
> +				};
> +
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					typec_con_ss: endpoint {
> +						remote-endpoint = <&usb3_data_ss>;
> +					};
> +				};

No SBU port?

> +			};
> +		};
> +	};
>  };
>  
>  &lcdif {
> @@ -445,6 +504,28 @@ &uart1 {
>  	status = "okay";
>  };
>  
> +&usb3_phy0 {
> +	status = "okay";
> +};
> +
> +&usb_dwc3_0 {
> +	dr_mode = "otg";
> +	hnp-disable;
> +	srp-disable;
> +	adp-disable;
> +	usb-role-switch;
> +	role-switch-default-mode = "none";
> +	snps,dis-u1-entry-quirk;
> +	snps,dis-u2-entry-quirk;
> +	status = "okay";
> +
> +	port {
> +		usb3_drd_sw: endpoint {
> +			remote-endpoint = <&typec_dr_sw>;
> +		};
> +	};
> +};
> +
>  &usb3_phy1 {
>  	status = "okay";
>  };
> @@ -597,6 +678,18 @@ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
>  		>;
>  	};
>  
> +	pinctrl_typec: typecgrp {
> +		fsl,pins = <
> +			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x17059
> +		>;
> +	};
> +
> +	pinctrl_typec_mux: typecmuxgrp {
> +		fsl,pins = <
> +			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x16
> +		>;
> +	};
> +
>  	pinctrl_uart1: uart1grp {
>  		fsl,pins = <
>  			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
> -- 
> 2.34.1
>
Xu Yang July 30, 2024, 3:08 a.m. UTC | #2 
On Mon, Jul 29, 2024 at 10:56:31PM +0300, Dmitry Baryshkov wrote:
> On Mon, Jul 29, 2024 at 04:10:39PM GMT, Xu Yang wrote:
> > The first port of USB with type-C connector, which has dual data
> > role and dual power role.
> > 
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 93 ++++++++++++++++++++
> >  1 file changed, 93 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > index 7507548cdb16..008e8c37c76b 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > @@ -6,6 +6,7 @@
> >  
> >  /dts-v1/;
> >  
> > +#include <dt-bindings/usb/pd.h>
> >  #include "imx8mq.dtsi"
> >  
> >  / {
> > @@ -27,6 +28,20 @@ pcie0_refclk: pcie0-refclk {
> >  		clock-frequency = <100000000>;
> >  	};
> >  
> > +	ptn36043: typec-mux {
> > +		compatible = "nxp,ptn36043", "gpio-sbu-mux";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_typec_mux>;
> > +		select-gpios =<&gpio3 15 GPIO_ACTIVE_LOW>;
> > +		orientation-switch;
> > +
> > +		port {
> > +			usb3_data_ss: endpoint {
> > +				remote-endpoint = <&typec_con_ss>;
> > +			};
> > +		};
> 
> If this the "SBU" mux, then why is it connected to the SS lines?
> Where are the SS lines further going?

The gpio-mux is able to switch SS line. ptn36043 is SS orientation
swich here.

> 
> > +	};
> > +
> >  	reg_pcie1: regulator-pcie {
> >  		compatible = "regulator-fixed";
> >  		pinctrl-names = "default";
> > @@ -315,6 +330,50 @@ vgen6_reg: vgen6 {
> >  			};
> >  		};
> >  	};
> > +
> > +	ptn5110: tcpc@50 {
> > +		compatible = "nxp,ptn5110", "tcpci";
> > +		reg = <0x50>;
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_typec>;
> > +		interrupt-parent = <&gpio3>;
> > +		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > +
> > +		usb_con: connector {
> > +			compatible = "usb-c-connector";
> > +			label = "USB-C";
> > +			power-role = "dual";
> > +			data-role = "dual";
> > +			try-power-role = "sink";
> > +			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
> > +			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
> > +				     PDO_VAR(5000, 20000, 3000)>;
> > +			op-sink-microwatt = <15000000>;
> > +			self-powered;
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				port@0 {
> > +					reg = <0>;
> > +
> > +					typec_dr_sw: endpoint {
> 
> the DR (dual role) isn't a physical signal. These ports descrbie HS
> (high speed) lanes, please consider naming them correspondingly.

Okay.

> 
> > +						remote-endpoint = <&usb3_drd_sw>;
> > +					};
> > +				};
> > +
> > +
> > +				port@1 {
> > +					reg = <1>;
> > +
> > +					typec_con_ss: endpoint {
> > +						remote-endpoint = <&usb3_data_ss>;
> > +					};
> > +				};
> 
> No SBU port?

Yes, this board doesn't use SBU signal.

Thanks,
Xu Yang

> 
> > +			};
> > +		};
> > +	};
> >  };
> >  
> >  &lcdif {
> > @@ -445,6 +504,28 @@ &uart1 {
> >  	status = "okay";
> >  };
> >  
> > +&usb3_phy0 {
> > +	status = "okay";
> > +};
> > +
> > +&usb_dwc3_0 {
> > +	dr_mode = "otg";
> > +	hnp-disable;
> > +	srp-disable;
> > +	adp-disable;
> > +	usb-role-switch;
> > +	role-switch-default-mode = "none";
> > +	snps,dis-u1-entry-quirk;
> > +	snps,dis-u2-entry-quirk;
> > +	status = "okay";
> > +
> > +	port {
> > +		usb3_drd_sw: endpoint {
> > +			remote-endpoint = <&typec_dr_sw>;
> > +		};
> > +	};
> > +};
> > +
> >  &usb3_phy1 {
> >  	status = "okay";
> >  };
> > @@ -597,6 +678,18 @@ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
> >  		>;
> >  	};
> >  
> > +	pinctrl_typec: typecgrp {
> > +		fsl,pins = <
> > +			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x17059
> > +		>;
> > +	};
> > +
> > +	pinctrl_typec_mux: typecmuxgrp {
> > +		fsl,pins = <
> > +			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x16
> > +		>;
> > +	};
> > +
> >  	pinctrl_uart1: uart1grp {
> >  		fsl,pins = <
> >  			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
> > -- 
> > 2.34.1
> > 
> 
> -- 
> With best wishes
> Dmitry
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 7507548cdb16..008e8c37c76b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -6,6 +6,7 @@ 
 
 /dts-v1/;
 
+#include <dt-bindings/usb/pd.h>
 #include "imx8mq.dtsi"
 
 / {
@@ -27,6 +28,20 @@  pcie0_refclk: pcie0-refclk {
 		clock-frequency = <100000000>;
 	};
 
+	ptn36043: typec-mux {
+		compatible = "nxp,ptn36043", "gpio-sbu-mux";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec_mux>;
+		select-gpios =<&gpio3 15 GPIO_ACTIVE_LOW>;
+		orientation-switch;
+
+		port {
+			usb3_data_ss: endpoint {
+				remote-endpoint = <&typec_con_ss>;
+			};
+		};
+	};
+
 	reg_pcie1: regulator-pcie {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -315,6 +330,50 @@  vgen6_reg: vgen6 {
 			};
 		};
 	};
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110", "tcpci";
+		reg = <0x50>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					typec_dr_sw: endpoint {
+						remote-endpoint = <&usb3_drd_sw>;
+					};
+				};
+
+
+				port@1 {
+					reg = <1>;
+
+					typec_con_ss: endpoint {
+						remote-endpoint = <&usb3_data_ss>;
+					};
+				};
+			};
+		};
+	};
 };
 
 &lcdif {
@@ -445,6 +504,28 @@  &uart1 {
 	status = "okay";
 };
 
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	role-switch-default-mode = "none";
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	status = "okay";
+
+	port {
+		usb3_drd_sw: endpoint {
+			remote-endpoint = <&typec_dr_sw>;
+		};
+	};
+};
+
 &usb3_phy1 {
 	status = "okay";
 };
@@ -597,6 +678,18 @@  MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
 		>;
 	};
 
+	pinctrl_typec: typecgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x17059
+		>;
+	};
+
+	pinctrl_typec_mux: typecmuxgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x16
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49