| Message ID | 20241029072444.8827-2-francesco@dolcini.it (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | USB: xhci: add support for PWRON polarity invert (TI TUSB73x0) | expand |
On Tue, Oct 29, 2024 at 08:24:43AM +0100, Francesco Dolcini wrote: > From: Parth Pancholi <parth.pancholi@toradex.com> > > Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI > host controller. The controller supports software configuration > through PCIe registers, such as controlling the PWRONx polarity > via the USB control register (E0h). > > Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> > --- > v5: > - s/ti,tusb7320-pwron-active-high/ti,pwron-active-high/ > v4: > - add $ref: usb-xhci.yaml > - description: wrap to 80 columns, add that the two variants use the > same device ID > - revise the example, based on comment from Rob and taking > marvell,prestera.yaml as an example (this binding was reviewed and > amended by Rob in the past). > v3: use lowercase hex in compatible > v2: rename property to ti,tusb7320-pwron-active-high and change type to flag Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml new file mode 100644 index 000000000000..ddda734f36fb --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) + +maintainers: + - Francesco Dolcini <francesco.dolcini@toradex.com> + +description: + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports up + to four downstream ports, both variants share the same PCI device ID. + +properties: + compatible: + const: pci104c,8241 + + reg: + maxItems: 1 + + ti,pwron-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the polarity of the PWRONx# signals. When this is present, the + PWRONx# pins are active high and their internal pull-down resistors are + disabled. When this is absent, the PWRONx# pins are active low (default) + and their internal pull-down resistors are enabled. + +required: + - compatible + - reg + +allOf: + - $ref: usb-xhci.yaml + +additionalProperties: false + +examples: + - | + pcie@0 { + reg = <0x0 0x1000>; + ranges = <0x02000000 0x0 0x100000 0x10000000 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + usb@0 { + compatible = "pci104c,8241"; + reg = <0x0 0x0 0x0 0x0 0x0>; + ti,pwron-active-high; + }; + };