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[35.247.103.198]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-72407a1fd2bsm1984909b3a.167.2024.11.07.11.31.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Nov 2024 11:31:51 -0800 (PST) From: Abhishek Pandit-Subedi To: heikki.krogerus@linux.intel.com, tzungbi@kernel.org, linux-usb@vger.kernel.org, chrome-platform@lists.linux.dev Cc: jthies@google.com, akuchynski@google.com, pmalani@chromium.org, dmitry.baryshkov@linaro.org, Abhishek Pandit-Subedi , Benson Leung , Guenter Roeck , linux-kernel@vger.kernel.org Subject: [PATCH v3 7/7] platform/chrome: cros_ec_typec: Disable tbt on port Date: Thu, 7 Nov 2024 11:30:00 -0800 Message-ID: <20241107112955.v3.7.Ic14738918e3d026fa2d85e95fb68f8e07a0828d0@changeid> X-Mailer: git-send-email 2.47.0.277.g8800431eea-goog In-Reply-To: <20241107193021.2690050-1-abhishekpandit@chromium.org> References: <20241107193021.2690050-1-abhishekpandit@chromium.org> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Altmodes with cros_ec are either automatically entered by the EC or entered by the AP if TBT or USB4 are supported on the system. Due to the security risk of PCIe tunneling, TBT modes should not be auto entered by the kernel at this time and will require user intervention. With this change, a userspace program will need to explicitly activate the thunderbolt mode on the port and partner in order to enter the mode and the thunderbolt driver will not automatically enter when a partner is connected. Signed-off-by: Abhishek Pandit-Subedi --- Changes in v3: - Set port.inactive = true instead of auto-enter. Changes in v2: - Only disable auto-enter for Thunderbolt - Update commit message to clearly indicate the need for userspace intervention to enter TBT mode drivers/platform/chrome/cros_ec_typec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index 558b618df63c..b01efe82fb1e 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -310,6 +310,7 @@ static int cros_typec_register_port_altmodes(struct cros_typec_data *typec, memset(&desc, 0, sizeof(desc)); desc.svid = USB_TYPEC_TBT_SID; desc.mode = TBT_MODE; + desc.inactive = true; amode = cros_typec_register_thunderbolt(port, &desc); if (IS_ERR(amode)) return PTR_ERR(amode);