| Message ID | 20241112091355.2028018-7-quic_varada@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable IPQ5424 USB support | expand |
On 11/12/2024 2:43 PM, Varadarajan Narayanan wrote: > The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0 > can connect to either of USB2.0 or USB3.0 phy and operate in the > respective mode. > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 67 +++++++++ > arch/arm64/boot/dts/qcom/ipq5424.dtsi | 153 ++++++++++++++++++++ > 2 files changed, 220 insertions(+) > [...] > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > index 5e219f900412..d8c045a311c2 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > @@ -233,6 +233,159 @@ intc: interrupt-controller@f200000 { > msi-controller; > }; > > + qusb_phy_1: phy@71000 { > + compatible = "qcom,ipq5424-qusb2-phy"; > + reg = <0 0x00071000 0 0x180>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > + <&xo_board>; > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; > + status = "disabled"; > + }; > + > + usb2: usb2@1e00000 { > + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; > + reg = <0 0x01ef8800 0 0x400>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB1_MASTER_CLK>, > + <&gcc GCC_USB1_SLEEP_CLK>, > + <&gcc GCC_USB1_MOCK_UTMI_CLK>, > + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > + <&gcc GCC_CNOC_USB_CLK>; > + > + clock-names = "core", > + "sleep", > + "mock_utmi", > + "iface", > + "cfg_noc"; > + > + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, > + <&gcc GCC_USB1_MOCK_UTMI_CLK>; > + assigned-clock-rates = <200000000>, > + <24000000>; > + Shouldn't this be 19.2MHz ? > + interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "pwr_event", > + "qusb2_phy", > + "dm_hs_phy_irq", > + "dp_hs_phy_irq"; > + Please check the hs_phy_irq as well and add it if its present. > + resets = <&gcc GCC_USB1_BCR>; > + qcom,select-utmi-as-pipe-clk; > + status = "disabled"; > + > + dwc_1: usb@1e00000 { > + compatible = "snps,dwc3"; > + reg = <0 0x01e00000 0 0xe000>; > + clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; > + clock-names = "ref"; Another clock in dwc3 node ? > + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&qusb_phy_1>; > + phy-names = "usb2-phy"; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + }; > + }; > + > + qusb_phy_0: phy@7b000 { > + compatible = "qcom,ipq5424-qusb2-phy"; > + reg = <0 0x0007b000 0 0x180>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&xo_board>; > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + status = "disabled"; > + }; > + > + ssphy_0: phy@7d000 { > + compatible = "qcom,ipq5424-qmp-usb3-phy"; > + reg = <0 0x0007d000 0 0xa00>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB0_AUX_CLK>, > + <&xo_board>, > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&gcc GCC_USB0_PIPE_CLK>; > + clock-names = "aux", > + "ref", > + "cfg_ahb", > + "pipe"; > + > + resets = <&gcc GCC_USB0_PHY_BCR>, > + <&gcc GCC_USB3PHY_0_PHY_BCR>; > + reset-names = "phy", > + "phy_phy"; > + > + #clock-cells = <0>; > + clock-output-names = "usb0_pipe_clk"; > + > + status = "disabled"; > + }; > + > + usb3: usb3@8a00000 { > + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; > + reg = <0 0x08af8800 0 0x400>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_USB0_SLEEP_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>, > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&gcc GCC_CNOC_USB_CLK>; > + > + clock-names = "core", > + "sleep", > + "mock_utmi", > + "iface", > + "cfg_noc"; > + > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + assigned-clock-rates = <200000000>, > + <24000000>; > + same comment as above, isn't this supposed to be 19.2MHz ? > + interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "pwr_event", > + "qusb2_phy"; > + DP/ DM interrupts ? > + resets = <&gcc GCC_USB_BCR>; > + status = "disabled"; > + > + dwc_0: usb@8a00000 { > + compatible = "snps,dwc3"; > + reg = <0 0x08a00000 0 0xcd00>; > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "ref"; > + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&qusb_phy_0>, <&ssphy_0>; > + phy-names = "usb2-phy", "usb3-phy"; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; Disable u1/u2 entry as well please. Regards, Krishna, > + }; > + }; > + > timer@f420000 { > compatible = "arm,armv7-timer-mem"; > reg = <0 0xf420000 0 0x1000>;
On Tue, Nov 12, 2024 at 03:05:57PM +0530, Krishna Kurapati wrote: > > > On 11/12/2024 2:43 PM, Varadarajan Narayanan wrote: > > The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0 > > can connect to either of USB2.0 or USB3.0 phy and operate in the > > respective mode. > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 67 +++++++++ > > arch/arm64/boot/dts/qcom/ipq5424.dtsi | 153 ++++++++++++++++++++ > > 2 files changed, 220 insertions(+) > > > > [...] > > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > index 5e219f900412..d8c045a311c2 100644 > > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > @@ -233,6 +233,159 @@ intc: interrupt-controller@f200000 { > > msi-controller; > > }; > > + qusb_phy_1: phy@71000 { > > + compatible = "qcom,ipq5424-qusb2-phy"; > > + reg = <0 0x00071000 0 0x180>; > > + #phy-cells = <0>; > > + > > + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > > + <&xo_board>; > > + clock-names = "cfg_ahb", "ref"; > > + > > + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; > > + status = "disabled"; > > + }; > > + > > + usb2: usb2@1e00000 { > > + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; > > + reg = <0 0x01ef8800 0 0x400>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + clocks = <&gcc GCC_USB1_MASTER_CLK>, > > + <&gcc GCC_USB1_SLEEP_CLK>, > > + <&gcc GCC_USB1_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > > + <&gcc GCC_CNOC_USB_CLK>; > > + > > + clock-names = "core", > > + "sleep", > > + "mock_utmi", > > + "iface", > > + "cfg_noc"; > > + > > + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, > > + <&gcc GCC_USB1_MOCK_UTMI_CLK>; > > + assigned-clock-rates = <200000000>, > > + <24000000>; > + > > Shouldn't this be 19.2MHz ? XO is 24MHz in this SoC. > > + interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pwr_event", > > + "qusb2_phy", > > + "dm_hs_phy_irq", > > + "dp_hs_phy_irq"; > > + > > Please check the hs_phy_irq as well and add it if its present. Will add. > > + resets = <&gcc GCC_USB1_BCR>; > > + qcom,select-utmi-as-pipe-clk; > > + status = "disabled"; > > + > > + dwc_1: usb@1e00000 { > > + compatible = "snps,dwc3"; > > + reg = <0 0x01e00000 0 0xe000>; > > + clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; > > + clock-names = "ref"; > > Another clock in dwc3 node ? > > > + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; > > + phys = <&qusb_phy_1>; > > + phy-names = "usb2-phy"; > > + tx-fifo-resize; > > + snps,is-utmi-l1-suspend; > > + snps,hird-threshold = /bits/ 8 <0x0>; > > + snps,dis_u2_susphy_quirk; > > + snps,dis_u3_susphy_quirk; > > + }; > > + }; > > + > > + qusb_phy_0: phy@7b000 { > > + compatible = "qcom,ipq5424-qusb2-phy"; > > + reg = <0 0x0007b000 0 0x180>; > > + #phy-cells = <0>; > > + > > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > + <&xo_board>; > > + clock-names = "cfg_ahb", "ref"; > > + > > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > > + status = "disabled"; > > + }; > > + > > + ssphy_0: phy@7d000 { > > + compatible = "qcom,ipq5424-qmp-usb3-phy"; > > + reg = <0 0x0007d000 0 0xa00>; > > + #phy-cells = <0>; > > + > > + clocks = <&gcc GCC_USB0_AUX_CLK>, > > + <&xo_board>, > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > + <&gcc GCC_USB0_PIPE_CLK>; > > + clock-names = "aux", > > + "ref", > > + "cfg_ahb", > > + "pipe"; > > + > > + resets = <&gcc GCC_USB0_PHY_BCR>, > > + <&gcc GCC_USB3PHY_0_PHY_BCR>; > > + reset-names = "phy", > > + "phy_phy"; > > + > > + #clock-cells = <0>; > > + clock-output-names = "usb0_pipe_clk"; > > + > > + status = "disabled"; > > + }; > > + > > + usb3: usb3@8a00000 { > > + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; > > + reg = <0 0x08af8800 0 0x400>; > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + clocks = <&gcc GCC_USB0_MASTER_CLK>, > > + <&gcc GCC_USB0_SLEEP_CLK>, > > + <&gcc GCC_USB0_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > + <&gcc GCC_CNOC_USB_CLK>; > > + > > + clock-names = "core", > > + "sleep", > > + "mock_utmi", > > + "iface", > > + "cfg_noc"; > > + > > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, > > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > + assigned-clock-rates = <200000000>, > > + <24000000>; > > + > > same comment as above, isn't this supposed to be 19.2MHz ? XO is 24MHz in this SoC. > > + interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, > > + <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pwr_event", > > + "qusb2_phy"; > > + > > DP/ DM interrupts ? Will add. > > + resets = <&gcc GCC_USB_BCR>; > > + status = "disabled"; > > + > > + dwc_0: usb@8a00000 { > > + compatible = "snps,dwc3"; > > + reg = <0 0x08a00000 0 0xcd00>; > > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > + clock-names = "ref"; > > + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; > > + phys = <&qusb_phy_0>, <&ssphy_0>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + tx-fifo-resize; > > + snps,is-utmi-l1-suspend; > > + snps,hird-threshold = /bits/ 8 <0x0>; > > + snps,dis_u2_susphy_quirk; > > + snps,dis_u3_susphy_quirk; > > Disable u1/u2 entry as well please. Will add. Thanks Varada
On Tue, Nov 12, 2024 at 05:35:13PM +0530, Varadarajan Narayanan wrote: > On Tue, Nov 12, 2024 at 03:05:57PM +0530, Krishna Kurapati wrote: > > > > > > On 11/12/2024 2:43 PM, Varadarajan Narayanan wrote: > > > The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0 > > > can connect to either of USB2.0 or USB3.0 phy and operate in the > > > respective mode. > > > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > > --- > > > arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 67 +++++++++ > > > arch/arm64/boot/dts/qcom/ipq5424.dtsi | 153 ++++++++++++++++++++ > > > 2 files changed, 220 insertions(+) > > > > > > > [...] > > > > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > > index 5e219f900412..d8c045a311c2 100644 > > > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > > > @@ -233,6 +233,159 @@ intc: interrupt-controller@f200000 { > > > msi-controller; > > > }; > > > + qusb_phy_1: phy@71000 { > > > + compatible = "qcom,ipq5424-qusb2-phy"; > > > + reg = <0 0x00071000 0 0x180>; > > > + #phy-cells = <0>; > > > + > > > + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > > > + <&xo_board>; > > > + clock-names = "cfg_ahb", "ref"; > > > + > > > + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; > > > + status = "disabled"; > > > + }; > > > + > > > + usb2: usb2@1e00000 { > > > + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; > > > + reg = <0 0x01ef8800 0 0x400>; > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + ranges; > > > + > > > + clocks = <&gcc GCC_USB1_MASTER_CLK>, > > > + <&gcc GCC_USB1_SLEEP_CLK>, > > > + <&gcc GCC_USB1_MOCK_UTMI_CLK>, > > > + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > > > + <&gcc GCC_CNOC_USB_CLK>; > > > + > > > + clock-names = "core", > > > + "sleep", > > > + "mock_utmi", > > > + "iface", > > > + "cfg_noc"; > > > + > > > + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, > > > + <&gcc GCC_USB1_MOCK_UTMI_CLK>; > > > + assigned-clock-rates = <200000000>, > > > + <24000000>; > + > > > > Shouldn't this be 19.2MHz ? > > XO is 24MHz in this SoC. > > > > + interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, > > > + <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, > > > + <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, > > > + <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "pwr_event", > > > + "qusb2_phy", > > > + "dm_hs_phy_irq", > > > + "dp_hs_phy_irq"; > > > + > > > > Please check the hs_phy_irq as well and add it if its present. > > Will add. Checked with HW team, there is no hs_phy_irq in this case. > > > + resets = <&gcc GCC_USB1_BCR>; > > > + qcom,select-utmi-as-pipe-clk; > > > + status = "disabled"; > > > + > > > + dwc_1: usb@1e00000 { > > > + compatible = "snps,dwc3"; > > > + reg = <0 0x01e00000 0 0xe000>; > > > + clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; > > > + clock-names = "ref"; > > > > Another clock in dwc3 node ? Not sure if I understand the above comment. Per bindings [1] a clock entry is expected in this node. 1 - https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/usb/snps,dwc3.yaml#n57 Thanks Varada > > > + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; > > > + phys = <&qusb_phy_1>; > > > + phy-names = "usb2-phy"; > > > + tx-fifo-resize; > > > + snps,is-utmi-l1-suspend; > > > + snps,hird-threshold = /bits/ 8 <0x0>; > > > + snps,dis_u2_susphy_quirk; > > > + snps,dis_u3_susphy_quirk; > > > + }; > > > + }; > > > + > > > + qusb_phy_0: phy@7b000 { > > > + compatible = "qcom,ipq5424-qusb2-phy"; > > > + reg = <0 0x0007b000 0 0x180>; > > > + #phy-cells = <0>; > > > + > > > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > > + <&xo_board>; > > > + clock-names = "cfg_ahb", "ref"; > > > + > > > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > > > + status = "disabled"; > > > + }; > > > + > > > + ssphy_0: phy@7d000 { > > > + compatible = "qcom,ipq5424-qmp-usb3-phy"; > > > + reg = <0 0x0007d000 0 0xa00>; > > > + #phy-cells = <0>; > > > + > > > + clocks = <&gcc GCC_USB0_AUX_CLK>, > > > + <&xo_board>, > > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > > + <&gcc GCC_USB0_PIPE_CLK>; > > > + clock-names = "aux", > > > + "ref", > > > + "cfg_ahb", > > > + "pipe"; > > > + > > > + resets = <&gcc GCC_USB0_PHY_BCR>, > > > + <&gcc GCC_USB3PHY_0_PHY_BCR>; > > > + reset-names = "phy", > > > + "phy_phy"; > > > + > > > + #clock-cells = <0>; > > > + clock-output-names = "usb0_pipe_clk"; > > > + > > > + status = "disabled"; > > > + }; > > > + > > > + usb3: usb3@8a00000 { > > > + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; > > > + reg = <0 0x08af8800 0 0x400>; > > > + > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + ranges; > > > + > > > + clocks = <&gcc GCC_USB0_MASTER_CLK>, > > > + <&gcc GCC_USB0_SLEEP_CLK>, > > > + <&gcc GCC_USB0_MOCK_UTMI_CLK>, > > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > > > + <&gcc GCC_CNOC_USB_CLK>; > > > + > > > + clock-names = "core", > > > + "sleep", > > > + "mock_utmi", > > > + "iface", > > > + "cfg_noc"; > > > + > > > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, > > > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > > + assigned-clock-rates = <200000000>, > > > + <24000000>; > > > + > > > > same comment as above, isn't this supposed to be 19.2MHz ? > > XO is 24MHz in this SoC. > > > > + interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, > > > + <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "pwr_event", > > > + "qusb2_phy"; > > > + > > > > DP/ DM interrupts ? > > Will add. > > > > + resets = <&gcc GCC_USB_BCR>; > > > + status = "disabled"; > > > + > > > + dwc_0: usb@8a00000 { > > > + compatible = "snps,dwc3"; > > > + reg = <0 0x08a00000 0 0xcd00>; > > > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > > > + clock-names = "ref"; > > > + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; > > > + phys = <&qusb_phy_0>, <&ssphy_0>; > > > + phy-names = "usb2-phy", "usb3-phy"; > > > + tx-fifo-resize; > > > + snps,is-utmi-l1-suspend; > > > + snps,hird-threshold = /bits/ 8 <0x0>; > > > + snps,dis_u2_susphy_quirk; > > > + snps,dis_u3_susphy_quirk; > > > > Disable u1/u2 entry as well please. > > Will add. > > Thanks > Varada >
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index d4d31026a026..3d50a419139d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -16,12 +16,71 @@ / { aliases { serial0 = &uart1; }; + + regulator_fixed_3p3: s3300 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_3p3"; + }; + + regulator_fixed_1p8: s1800 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_1p8"; + }; + + regulator_fixed_0p925: s0925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_0p925"; + }; + +}; + +&dwc_0 { + dr_mode = "host"; +}; + +&dwc_1 { + dr_mode = "host"; +}; + +&qusb_phy_0 { + vdd-supply = <®ulator_fixed_0p925>; + vdda-pll-supply = <®ulator_fixed_1p8>; + vdda-phy-dpdm-supply = <®ulator_fixed_3p3>; + + status = "okay"; +}; + +&qusb_phy_1 { + vdd-supply = <®ulator_fixed_0p925>; + vdda-pll-supply = <®ulator_fixed_1p8>; + vdda-phy-dpdm-supply = <®ulator_fixed_3p3>; + + status = "okay"; }; &sleep_clk { clock-frequency = <32000>; }; +&ssphy_0 { + vdda-pll-supply = <®ulator_fixed_1p8>; + vdda-phy-supply = <®ulator_fixed_0p925>; + + status = "okay"; +}; + &tlmm { sdc_default_state: sdc-default-state { clk-pins { @@ -53,6 +112,14 @@ &uart1 { status = "okay"; }; +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + &xo_board { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 5e219f900412..d8c045a311c2 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -233,6 +233,159 @@ intc: interrupt-controller@f200000 { msi-controller; }; + qusb_phy_1: phy@71000 { + compatible = "qcom,ipq5424-qusb2-phy"; + reg = <0 0x00071000 0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo_board>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; + status = "disabled"; + }; + + usb2: usb2@1e00000 { + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; + reg = <0 0x01ef8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>, + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&gcc GCC_CNOC_USB_CLK>; + + clock-names = "core", + "sleep", + "mock_utmi", + "iface", + "cfg_noc"; + + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + resets = <&gcc GCC_USB1_BCR>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + dwc_1: usb@1e00000 { + compatible = "snps,dwc3"; + reg = <0 0x01e00000 0 0xe000>; + clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_1>; + phy-names = "usb2-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + + qusb_phy_0: phy@7b000 { + compatible = "qcom,ipq5424-qusb2-phy"; + reg = <0 0x0007b000 0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible = "qcom,ipq5424-qmp-usb3-phy"; + reg = <0 0x0007d000 0 0xa00>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&xo_board>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + + status = "disabled"; + }; + + usb3: usb3@8a00000 { + compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; + reg = <0 0x08af8800 0 0x400>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_CNOC_USB_CLK>; + + clock-names = "core", + "sleep", + "mock_utmi", + "iface", + "cfg_noc"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy"; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0 0x08a00000 0 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_0>, <&ssphy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + timer@f420000 { compatible = "arm,armv7-timer-mem"; reg = <0 0xf420000 0 0x1000>;
The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0 can connect to either of USB2.0 or USB3.0 phy and operate in the respective mode. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 67 +++++++++ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 153 ++++++++++++++++++++ 2 files changed, 220 insertions(+)