From patchwork Wed Feb 12 19:28:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13972366 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F2FB1DC07D; Wed, 12 Feb 2025 19:31:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739388685; cv=none; b=hCYxvoRkA6AF8nMeBHy1/gDLA+vRiSJmO/k/wdygJfvWqlgfXo6+ae9iqLI0tkz8SYMR9SUUQDe18yORRe0g1gYpXOZZ6FXBJc2RnMk8genuceknbcwtsF+ZZWEMKdRH8aaFAxCn8qbJ5qh5tLDIaJ4lwXZQUACLBVb9LT1Qs4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739388685; c=relaxed/simple; bh=QWfCk6Z9kmUwiT/DGt2f/lMajzR81wKfnu7GN46kOys=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iYz6VxkNP70FAIXQtSkset7utj5BENSeLTbnQivapyrnYxEKGJu9Oig2RdGAXiB3FqNBzn2uEykqANxlCjj9VseqM9Nq4xz4RcXPtQOHKPaNWXp2cla8/dLs42txXBd4SCkjJ/fRw3gFGWAuKSFe6NgV3FzcbCtSFGG2apQ4QCc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RHV+S7FJ; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RHV+S7FJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739388684; x=1770924684; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QWfCk6Z9kmUwiT/DGt2f/lMajzR81wKfnu7GN46kOys=; b=RHV+S7FJEOX5oTeFqrx7iWPTcTnXKbQ8HuMCZsumt9lRVAabuttsCqC+ E6eXUKGhENQCLT323h0J3f4juLhH8v9atWgUK2TWUCWSlEXQfiw7OXtLz jJFmnBXU3bYsqFfvItYLSQD1BfbgOrQu7QnZA02Sngnowxuc50qcvSGVk MkrsrpF3xvedLXN5NDbvGs23v5QzeDWSHP0LjkxYscVoMHUIQaZ+MGLUy xOgq7XZWA1Ub5tJfHUHMN2pIYKX9m2P+4dI3llY+67GpxaLU65RMBuSBk jSimWopJ/fTNE2m/6RMbwPmM0RqRM+3tMnxoK7Z/+6QdYaOhnlf+3jUAA A==; X-CSE-ConnectionGUID: abR/tZHXQaqBourjndWzFQ== X-CSE-MsgGUID: GlGls5kWSB2E8Bf3D3/Qng== X-IronPort-AV: E=McAfee;i="6700,10204,11343"; a="50714405" X-IronPort-AV: E=Sophos;i="6.13,280,1732608000"; d="scan'208";a="50714405" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2025 11:31:24 -0800 X-CSE-ConnectionGUID: Oi6g4VVQRSWYiCtLZuw10A== X-CSE-MsgGUID: SalJIseoSXmw88IeDLGjrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,280,1732608000"; d="scan'208";a="112880548" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa006.jf.intel.com with ESMTP; 12 Feb 2025 11:31:21 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 7F3C531C; Wed, 12 Feb 2025 21:31:19 +0200 (EET) From: Andy Shevchenko To: Greg Kroah-Hartman , Thinh Nguyen , Felipe Balbi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , Ferry Toth Subject: [PATCH v3 4/4] usb: dwc3: gadget: Avoid using reserved endpoints on Intel Merrifield Date: Wed, 12 Feb 2025 21:28:04 +0200 Message-ID: <20250212193116.2487289-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.45.1.3035.g276e886db78b In-Reply-To: <20250212193116.2487289-1-andriy.shevchenko@linux.intel.com> References: <20250212193116.2487289-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Intel Merrifield SoC uses these endpoints for tracing and they cannot be re-allocated if being used because the side band flow control signals are hard wired to certain endpoints: • 1 High BW Bulk IN (IN#1) (RTIT) • 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8) In device mode, since RTIT (EP#1) and EXI/RunControl (EP#8) uses External Buffer Control (EBC) mode, these endpoints are to be mapped to EBC mode (to be done by EXI target driver). Additionally TRB for RTIT and EXI are maintained in STM (System Trace Module) unit and the EXI target driver will as well configure the TRB location for EP #1 IN and EP#8 (IN and OUT). Since STM/PTI and EXI hardware blocks manage these endpoints and interface to OTG3 controller through EBC interface, there is no need to enable any events (such as XferComplete etc) for these end points. Signed-off-by: Andy Shevchenko Tested-by: Ferry Toth Acked-by: Thinh Nguyen --- drivers/usb/dwc3/dwc3-pci.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index 052852f80146..54a4ee2b90b7 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -148,11 +148,21 @@ static const struct property_entry dwc3_pci_intel_byt_properties[] = { {} }; +/* + * Intel Merrifield SoC uses these endpoints for tracing and they cannot + * be re-allocated if being used because the side band flow control signals + * are hard wired to certain endpoints: + * - 1 High BW Bulk IN (IN#1) (RTIT) + * - 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8) + */ +static const u8 dwc3_pci_mrfld_reserved_endpoints[] = { 3, 16, 17 }; + static const struct property_entry dwc3_pci_mrfld_properties[] = { PROPERTY_ENTRY_STRING("dr_mode", "otg"), PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), + PROPERTY_ENTRY_U8_ARRAY("snps,reserved-endpoints", dwc3_pci_mrfld_reserved_endpoints), PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), {}