From patchwork Tue Mar 18 19:05:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 14021440 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC8BE212B34 for ; Tue, 18 Mar 2025 19:05:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742324716; cv=none; b=JaSsvUBnJioXQ4obVUV0G/WoTJgCXme8zWpwv+cdyCHL7RhHlITeoOyWee1zzi7DFGOsZ7rftzA+wtXBFGNNw0scL1/ruKYEOu4ecmm+RBdJID7xXzI1TkL7cWUVRUGO3MgS2O5NxP0DtMYx+h0TxadMYwM3FTa0G5nQcO0f41E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742324716; c=relaxed/simple; bh=DEqG6H+cOl1vDt9TUURWPPhC7aIVbXIcgwz9taU6ZdY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W/7OJiId/nA8cKf2wPX0Nfg6911LsaPDzVteoNNuLiIPQMzIk2PlOcFkFSfPmcTsebI6thF8UnwQGK9e98Sqki74vEmKxXsV+XHg5DkBpvbw/3pQYUuajLiWpi+5ToilpXdP7PBmcjVPnKHJ3jlCxeS4R33NpXM2ngn6rfKFCgA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=goZc8X2z; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="goZc8X2z" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52IAWsIK010361 for ; Tue, 18 Mar 2025 19:05:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 15GtEClxEwnKXqYU1WrImvfV9ZaBP1dLQTSncNs+VgU=; b=goZc8X2z94qDx1Kl IYLAS0A26dsIhc2Wy5qH1briUbEWGGPwhEXctoKDZiFWGfmZ0EvOzbZmy1J1McpJ 7+WW2vUoKtBGJket+jHujeV8N01GLlF2Efxm5CGU6xe6YjZfWWMK39rhDLtgw0yh cPrynKJs3PMezGNFO1EFklsdCGIiZJ6xsjqDAk+5YfWlFmAebH7gvTGsd1IfsjCJ iXsKPnxmReG9tQ7Z5a4wNYTKYmV4jOf0M5pEf8l+BSsg0J6oVvhNtcnPvozvk9Ir NWoFDFzzl1hrq6cdUBJQzKkPwo/aJ4Fc8hz00pm/E0twJrKko2RBS7JF/4hetCMh c+opYw== Received: from mail-oi1-f200.google.com (mail-oi1-f200.google.com [209.85.167.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45exx32yfc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 18 Mar 2025 19:05:13 +0000 (GMT) Received: by mail-oi1-f200.google.com with SMTP id 5614622812f47-3f99583b44aso5127584b6e.0 for ; Tue, 18 Mar 2025 12:05:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742324713; x=1742929513; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=15GtEClxEwnKXqYU1WrImvfV9ZaBP1dLQTSncNs+VgU=; b=fKMG+Xw5NqKgEuDMnsVXPn+oB4H7hxjQS2x3b7mMnSVFZfZGL4ky25tbTeJvOBlV7r Q7wcooIHZQIiJICigrbfv7qegwJ00zQLtG50wd9V4P7lWSF9UmSOiBY7x0a6GB2y04lu La2cio7Nywn/MWOv1Bl2mQYE1Qj+WaOeIhm0xPoP+Lhu+A3Z2qnyys/E9unfMu10sqNg Z57UWSQSddUCZhouRI2uBju0rdl9vDjcpMGGYtEi0rLTW/B1Q4Av2NSwTllJIc0x3hGO 9Czq/E/ptr3xSHflH/4ccD7lXtdw83JAymkP8tJjPZXMuY3lp/0TjF69txXIXljRffnO Y9Fw== X-Forwarded-Encrypted: i=1; AJvYcCVuh8u7EvGcgNd5t3b5ernvnxqNxHTmXnHmOsWBTjvdtgWVR9HQ3sUARzt+qnmOzki4dAT/zVUJMeg=@vger.kernel.org X-Gm-Message-State: AOJu0Yz304KRo+EXFIB3o98obxqUuQULi/CGQNb/7CgpKB8xMn/1toW9 VBVvyGV5KEAU7PX6cIev6bDa4X/7B6gq5yGVDoZwg2xn6zGswciRsR8fNrPpmc27YZaLAARGfU3 vOsmZNStDY7xNrmmIBffvEvqajgzz1gagKXqQNUI7ZbBMSNH3+sjH/jXsx70= X-Gm-Gg: ASbGncsrGVslzTyxhxdrshOeztomoqDOqo1vphub3W7KLa+k+y1h9YjG9Fp/xehGb79 AFEv1aG2UGY6DFj8XEE1A0VLvYe9/ObOhJitBtz62Qqu/0tHRLICYPPGvhEGtD/mG4v69ZpV2QE uDw03rRoyHgC+XBs8LZL3ePip12zGD+BFL7QEq2EAlNJjnSnxjQEQevzG/5uPBZi7tF/rYIH1bG ct7XvrMdgmMvS7N6ARnVNhmB/VtDMqzjogLqwj3Pqy+tOQ+aISPflDjWJ1pAyyxj18PJLLqkW4d d1Jmt6/wbru7UpuIZ0Wx+NmVIJYnizk5XmYyDPqKQiLSZli9RtmJFTREmERjDPYh73W8gZBu9Ka mWYg4pXV9UqIEATs= X-Received: by 2002:a05:6808:1a10:b0:3fa:d6c:cdb5 with SMTP id 5614622812f47-3fdf0647255mr9164502b6e.34.1742324712601; Tue, 18 Mar 2025 12:05:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHG3OG/orn8Ryioc+1Xj7hZDUvKd3LKjQUvXiCbJuah4wZJsHi2/ftlknr3hhvr1QajDJ9wvg== X-Received: by 2002:a05:6808:1a10:b0:3fa:d6c:cdb5 with SMTP id 5614622812f47-3fdf0647255mr9164467b6e.34.1742324712160; Tue, 18 Mar 2025 12:05:12 -0700 (PDT) Received: from [192.168.86.65] (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3fcd403b065sm2264273b6e.4.2025.03.18.12.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 12:05:11 -0700 (PDT) From: Bjorn Andersson Date: Tue, 18 Mar 2025 14:05:02 -0500 Subject: [PATCH v5 2/7] dt-bindings: usb: Introduce qcom,snps-dwc3 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250318-dwc3-refactor-v5-2-90ea6e5b3ba4@oss.qualcomm.com> References: <20250318-dwc3-refactor-v5-0-90ea6e5b3ba4@oss.qualcomm.com> In-Reply-To: <20250318-dwc3-refactor-v5-0-90ea6e5b3ba4@oss.qualcomm.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Wesley Cheng , Saravana Kannan , Thinh Nguyen , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Frank Li Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=19850; i=bjorn.andersson@oss.qualcomm.com; h=from:subject:message-id; bh=DEqG6H+cOl1vDt9TUURWPPhC7aIVbXIcgwz9taU6ZdY=; b=owEBgwJ8/ZANAwAIAQsfOT8Nma3FAcsmYgBn2cPjhmwG3xmdqVOu+v4y+X5suoKCYczs15mNE LUCasdc1XeJAkkEAAEIADMWIQQF3gPMXzXqTwlm1SULHzk/DZmtxQUCZ9nD4xUcYW5kZXJzc29u QGtlcm5lbC5vcmcACgkQCx85Pw2ZrcVhUg//btjGOTCyfeHLqse8yK5LbxZkz5XxR8DmRu+WylC /SAXb31TUaQAYNyOUZJza2r9NJM8IMuIRMfdhcLs9FFx1SuTM+Zg+sWZh+/lNFKceYlcTGOE7t9 1mMynVeScB6Ioko+ckxOLhvzgW9jH0eVElwxmaseR4TgRXqPUrJb7ep8xBMiDpawFRYNVVwtnKK 4yBHzbh8CgDSJ/5GYMc9o8smN03AidJrrWDmklsr6dNs/9cpBRzrrRf3oMsUmCoZJojNbnbrbEv cCHBy6ZK+V36lZT+KD4lqyHPFg2835xL4wjIHEdzHLjkuLmWVXTZIV1UsyvOXSamRTB9ilRz+zN ruceUwCbzmpnG/4BNNqR64TVi8OZbY4fqr9sHWQVHYI+xhh5Y9Lewib6ahIRxLtvQiF6WvL5nV6 dd6Q9TvLT4jomxC4OMTveekhNZHQJXFLnzcx6ORlR9a30qmJddutpbzHcqdp1oV9cT1S/pA3S24 YogaX7xOl8tAXdIdLPEJSB3upemxAifi1JRWpW+eA2Mp7gRuD2Tg4sGiwOecd3Izx2qgVTtNybz /zV/UCfJheOxYlhXDJf8z1Z7fFZ3MyMZmTr58MPr9iYJRhBmuoj3W73HTKeDEvAah0OioojI09q Jfa+RQvyWwe32HUG/9/MsMi+iAET/wsWwDgNmn8oTFsI= X-Developer-Key: i=bjorn.andersson@oss.qualcomm.com; a=openpgp; fpr=05DE03CC5F35EA4F0966D5250B1F393F0D99ADC5 X-Authority-Analysis: v=2.4 cv=b+uy4sGx c=1 sm=1 tr=0 ts=67d9c3e9 cx=c_pps a=AKZTfHrQPB8q3CcvmcIuDA==:117 a=DaeiM5VmU20ml6RIjrOvYw==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=sxEQ-6IQeHkip0RCg1sA:9 a=QEXdDO2ut3YA:10 a=pF_qn-MSjDawc0seGVz6:22 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 12l6iIEg59GKk1XnLUgR3PhrlfPmj2pV X-Proofpoint-GUID: 12l6iIEg59GKk1XnLUgR3PhrlfPmj2pV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_08,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 mlxscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180137 The Qualcomm USB glue is not separate of the Synopsys DWC3 core and several of the snps,dwc3 properties (such as clocks and reset) conflicts in expectation with the Qualcomm integration. Using the newly split out Synopsys DWC3 core properties, describe the Qualcomm USB block in a single block. The new binding is a copy of qcom,dwc3 with the needed modifications. It would have been convenient to retain the two structures with the same compatibles, but as there exist no way to select a binding based on the absence of a subnode/patternProperty, a new generic compatible is introduced to describe this binding. To avoid redefining all the platform-specific compatibles, "select" is used to tell the DeviceTree validator which binding to use solely on the generic compatible. (Otherwise if the specific compatible matches during validation, the generic one must match as well) Mark qcom,dwc3 deprecated, to favor expressing future platforms using the new combined binding. Signed-off-by: Bjorn Andersson Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 13 +- .../devicetree/bindings/usb/qcom,snps-dwc3.yaml | 620 +++++++++++++++++++++ 2 files changed, 632 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 64137c1619a635a5a4f96fc49bd75c5fb757febb..ffb8f9c654b7ae6c3ff29ead24bfe1e721d25afc 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -4,11 +4,22 @@ $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm SuperSpeed DWC3 USB SoC controller +title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller maintainers: - Wesley Cheng +# Use the combined qcom,snps-dwc3 instead +deprecated: true + +select: + properties: + compatible: + contains: + const: qcom,dwc3 + required: + - compatible + properties: compatible: items: diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml new file mode 100644 index 0000000000000000000000000000000000000000..85e1fa340c7a361bc49e0ca2d8b1a9bcad9e93a0 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml @@ -0,0 +1,620 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SuperSpeed DWC3 USB SoC controller + +maintainers: + - Wesley Cheng + +description: + Describes the Qualcomm USB block, based on Synopsys DWC3. + +select: + properties: + compatible: + contains: + const: qcom,snps-dwc3 + required: + - compatible + +properties: + compatible: + items: + - enum: + - qcom,ipq4019-dwc3 + - qcom,ipq5018-dwc3 + - qcom,ipq5332-dwc3 + - qcom,ipq5424-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8064-dwc3 + - qcom,ipq8074-dwc3 + - qcom,ipq9574-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8994-dwc3 + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,qcm2290-dwc3 + - qcom,qcs404-dwc3 + - qcom,qcs615-dwc3 + - qcom,qcs8300-dwc3 + - qcom,qdu1000-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sar2130p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8180x-dwc3-mp + - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp + - qcom,sdm660-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + - qcom,sm6350-dwc3 + - qcom,sm6375-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + - qcom,x1e80100-dwc3 + - const: qcom,snps-dwc3 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + required-opps: + maxItems: 1 + + clocks: + description: | + Several clocks are used, depending on the variant. Typical ones are:: + - cfg_noc:: System Config NOC clock. + - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= + 60MHz for HS operation. + - iface:: System bus AXI clock. + - sleep:: Sleep clock, used for wakeup when USB3 core goes into low + power mode (U3). + - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host + mode. Its frequency should be 19.2MHz. + minItems: 1 + maxItems: 9 + + clock-names: + minItems: 1 + maxItems: 9 + + iommus: + maxItems: 1 + + resets: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: usb-ddr + - const: apps-usb + + interrupts: + description: | + Different types of interrupts are used based on HS PHY used on target: + - dwc_usb3: Core DWC3 interrupt + - pwr_event: Used for wakeup based on other power events. + - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is + hs_phy_irq which is not triggered by default and its + functionality is mutually exclusive to that of + {dp/dm}_hs_phy_irq and qusb2_phy_irq. + - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and + expose only a single IRQ whose behavior can be modified + by the QUSB2PHY_INTR_CTRL register. The required DPSE/ + DMSE configuration is done in QUSB2PHY_INTR_CTRL register + of PHY address space. + - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ + DM pads of the SoC. These are used for wakeup + only on SoCs with non-QUSB2 targets with + exception of SDM670/SDM845/SM6350. + - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. + minItems: 3 + maxItems: 19 + + interrupt-names: + minItems: 3 + maxItems: 19 + + qcom,select-utmi-as-pipe-clk: + description: + If present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + type: boolean + + wakeup-source: true + +# Required child node: + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +allOf: + - $ref: snps,dwc3-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq4019-dwc3 + - qcom,ipq5332-dwc3 + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8064-dwc3 + then: + properties: + clocks: + items: + - description: Master/Core clock, has to be >= 125 MHz + for SS operation and >= 60MHz for HS operation. + clock-names: + items: + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,qcs8300-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm6350-dwc3 + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-dwc3 + then: + properties: + clocks: + minItems: 3 + maxItems: 4 + clock-names: + oneOf: + - items: + - const: core + - const: sleep + - const: mock_utmi + - items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-dwc3 + - qcom,qdu1000-dwc3 + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-dwc3 + - qcom,msm8994-dwc3 + - qcom,qcs404-dwc3 + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: core + - const: iface + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp + - qcom,x1e80100-dwc3 + - qcom,x1e80100-dwc3-mp + then: + properties: + clocks: + maxItems: 9 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: noc_aggr + - const: noc_aggr_north + - const: noc_aggr_south + - const: noc_sys + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm660-dwc3 + then: + properties: + clocks: + minItems: 4 + maxItems: 5 + clock-names: + oneOf: + - items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-dwc3 + - qcom,qcs615-dwc3 + - qcom,sar2130p-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8180x-dwc3-mp + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + then: + properties: + clocks: + minItems: 6 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: xo + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8350-dwc3 + then: + properties: + clocks: + minItems: 5 + maxItems: 6 + clock-names: + minItems: 5 + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: xo + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8074-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8998-dwc3 + then: + properties: + interrupts: + minItems: 3 + maxItems: 4 + interrupt-names: + minItems: 3 + items: + - const: dwc_usb3 + - const: pwr_event + - const: qusb2_phy + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-dwc3 + - qcom,qcs404-dwc3 + - qcom,sdm660-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + then: + properties: + interrupts: + minItems: 4 + maxItems: 5 + interrupt-names: + minItems: 4 + items: + - const: dwc_usb3 + - const: pwr_event + - const: qusb2_phy + - const: hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-dwc3 + then: + properties: + interrupts: + maxItems: 4 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-dwc3 + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq4019-dwc3 + - qcom,ipq8064-dwc3 + - qcom,msm8994-dwc3 + - qcom,qcs615-dwc3 + - qcom,qcs8300-dwc3 + - qcom,qdu1000-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8280xp-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6350-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + then: + properties: + interrupts: + minItems: 5 + maxItems: 6 + interrupt-names: + minItems: 5 + items: + - const: dwc_usb3 + - const: pwr_event + - const: hs_phy_irq + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-dwc3-mp + - qcom,x1e80100-dwc3-mp + then: + properties: + interrupts: + minItems: 11 + maxItems: 11 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event_1 + - const: pwr_event_2 + - const: hs_phy_1 + - const: hs_phy_2 + - const: dp_hs_phy_1 + - const: dm_hs_phy_1 + - const: dp_hs_phy_2 + - const: dm_hs_phy_2 + - const: ss_phy_1 + - const: ss_phy_2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3-mp + then: + properties: + interrupts: + minItems: 19 + maxItems: 19 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event_1 + - const: pwr_event_2 + - const: pwr_event_3 + - const: pwr_event_4 + - const: hs_phy_1 + - const: hs_phy_2 + - const: hs_phy_3 + - const: hs_phy_4 + - const: dp_hs_phy_1 + - const: dm_hs_phy_1 + - const: dp_hs_phy_2 + - const: dm_hs_phy_2 + - const: dp_hs_phy_3 + - const: dm_hs_phy_3 + - const: dp_hs_phy_4 + - const: dm_hs_phy_4 + - const: ss_phy_1 + - const: ss_phy_2 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + usb@a600000 { + compatible = "qcom,sdm845-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0x100000>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = , + , + , + , + , + ; + interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; +...