| Message ID | 20250331215720.19692-2-alex.vinarskis@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | X1E Asus Zenbook A14 support | expand |
On 3/31/25 11:53 PM, Aleksandrs Vinarskis wrote: > It appears at least on some devices (Asus Zenbook A14, x1-26-100) change > of pcie6a_phy's compatible breaks the controller. Move compatible change > from generic x1p42100.dtsi to CRD's specific x1p42100-crd.dts instead. > > Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> > --- > arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 ++++ > arch/arm64/boot/dts/qcom/x1p42100.dtsi | 4 ---- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts > index cf07860a63e9..a2a212b31556 100644 > --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts > +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts > @@ -15,3 +15,7 @@ / { > model = "Qualcomm Technologies, Inc. X1P42100 CRD"; > compatible = "qcom,x1p42100-crd", "qcom,x1p42100"; > }; > + > +&pcie6a_phy { > + compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi > index 27f479010bc3..4424a8708d39 100644 > --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi > @@ -37,10 +37,6 @@ &pcie3 { > num-lanes = <4>; > }; > > -&pcie6a_phy { > - compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; > -}; This is not correct. The hardware is different in all SoCs, not just the ones put in the CRD. You're probably missing this change [1], please test it out and leave a t-b if it's confirmed working for you. Konrad [1] https://lore.kernel.org/linux-arm-msm/4c7059a0-46a0-424d-9068-60894c6cec1c@quicinc.com/T/#m9675593a62b2334ab2afd4269da6938464a03fa6
On Tue, 1 Apr 2025 at 12:19, Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote: > > On 3/31/25 11:53 PM, Aleksandrs Vinarskis wrote: > > It appears at least on some devices (Asus Zenbook A14, x1-26-100) change > > of pcie6a_phy's compatible breaks the controller. Move compatible change > > from generic x1p42100.dtsi to CRD's specific x1p42100-crd.dts instead. > > > > Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> > > --- > > arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 ++++ > > arch/arm64/boot/dts/qcom/x1p42100.dtsi | 4 ---- > > 2 files changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts > > index cf07860a63e9..a2a212b31556 100644 > > --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts > > +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts > > @@ -15,3 +15,7 @@ / { > > model = "Qualcomm Technologies, Inc. X1P42100 CRD"; > > compatible = "qcom,x1p42100-crd", "qcom,x1p42100"; > > }; > > + > > +&pcie6a_phy { > > + compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; > > +}; > > diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi > > index 27f479010bc3..4424a8708d39 100644 > > --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi > > +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi > > @@ -37,10 +37,6 @@ &pcie3 { > > num-lanes = <4>; > > }; > > > > -&pcie6a_phy { > > - compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; > > -}; > > > This is not correct. The hardware is different in all SoCs, not just the > ones put in the CRD. > > You're probably missing this change [1], please test it out and leave a t-b > if it's confirmed working for you. Thanks for the pointer, with the missing peace it indeed works now! Left t-b. Will drop this change on re-spin later today. Thanks for the review, Alex > > Konrad > > [1] https://lore.kernel.org/linux-arm-msm/4c7059a0-46a0-424d-9068-60894c6cec1c@quicinc.com/T/#m9675593a62b2334ab2afd4269da6938464a03fa6
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts index cf07860a63e9..a2a212b31556 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts @@ -15,3 +15,7 @@ / { model = "Qualcomm Technologies, Inc. X1P42100 CRD"; compatible = "qcom,x1p42100-crd", "qcom,x1p42100"; }; + +&pcie6a_phy { + compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi index 27f479010bc3..4424a8708d39 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi @@ -37,10 +37,6 @@ &pcie3 { num-lanes = <4>; }; -&pcie6a_phy { - compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; -}; - &soc { /* The PCIe3 PHY on X1P42100 uses a different IP block */ pcie3_phy: phy@1bd4000 {
It appears at least on some devices (Asus Zenbook A14, x1-26-100) change of pcie6a_phy's compatible breaks the controller. Move compatible change from generic x1p42100.dtsi to CRD's specific x1p42100-crd.dts instead. Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> --- arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 ++++ arch/arm64/boot/dts/qcom/x1p42100.dtsi | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-)