From patchwork Wed Jun 7 10:56:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13270419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FC55C7EE2E for ; Wed, 7 Jun 2023 11:00:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239829AbjFGLAZ (ORCPT ); Wed, 7 Jun 2023 07:00:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240453AbjFGLAH (ORCPT ); Wed, 7 Jun 2023 07:00:07 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B9441BF7; Wed, 7 Jun 2023 03:58:44 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3575Li4h019759; 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Wed, 7 Jun 2023 10:57:05 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 7 Jun 2023 03:56:56 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH 4/9] clk: qcom: ipq5332: Fix USB related clock defines Date: Wed, 7 Jun 2023 16:26:08 +0530 Message-ID: <3840e5b5795ef55ecbf25d0faa8c328f09c6d976.1686126439.git.quic_varada@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Z2TsTwjIBn2S3qlWPRVHa0LxQyJiosUC X-Proofpoint-ORIG-GUID: Z2TsTwjIBn2S3qlWPRVHa0LxQyJiosUC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_06,2023-06-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 phishscore=0 suspectscore=0 priorityscore=1501 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306070089 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Fix the USB related clock defines and add details referenced by them Signed-off-by: Varadarajan Narayanan --- drivers/clk/qcom/gcc-ipq5332.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index a75ab88..2b58558 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -351,6 +351,16 @@ static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = { { } }; +static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = { + { .fw_name = "usb3phy_0_cc_pipe_clk" }, + { .fw_name = "xo" }, +}; + +static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { + { P_USB3PHY_0_PIPE, 0 }, + { P_XO, 2 }, +}; + static struct clk_rcg2 gcc_adss_pwm_clk_src = { .cmd_rcgr = 0x1c004, .mnd_width = 0, @@ -1101,16 +1111,18 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = { }, }; -static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { +static struct clk_regmap_mux usb0_pipe_clk_src = { .reg = 0x2c074, + .shift = 8, + .width = 2, + .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, .clkr = { - .hw.init = &(struct clk_init_data) { - .name = "gcc_usb0_pipe_clk_src", - .parent_data = &(const struct clk_parent_data) { - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, - }, - .num_parents = 1, - .ops = &clk_regmap_phy_mux_ops, + .hw.init = &(const struct clk_init_data){ + .name = "usb0phy_0_cc_pipe_clk_src", + .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, + .num_parents = 2, + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, }, }, }; @@ -3041,8 +3053,8 @@ static struct clk_branch gcc_usb0_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_usb0_pipe_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_usb0_pipe_clk_src.clkr.hw, + .parent_names = (const char *[]){ + "usb0_pipe_clk_src" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3580,7 +3592,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr, [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr, [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr, - [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, + [GCC_USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, }; static const struct qcom_reset_map gcc_ipq5332_resets[] = {