| Message ID | PH7PR07MB9538959C61B32EBCA33D1909DDB72@PH7PR07MB9538.namprd07.prod.outlook.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | usb: cdnsp: Fix issue with resuming from L1 | expand |
On Thu, Apr 10, 2025 at 07:34:16AM +0000, Pawel Laszczak wrote: > Subject: [PATCH] usb: cdnsp: Fix issue with resuming from L1 Why is the subject line duplicated here? Can you fix up your git send-email process to not do that? > In very rare cases after resuming controller from L1 to L0 it reads > registers before the clock has been enabled and as the result driver > reads incorrect value. > To fix this issue driver increases APB timeout value. > > Probably this issue occurs only on Cadence platform but fix > should have no impact for other existing platforms. If this is the case, shouldn't you just handle this for Cadence-specific hardware and add the check for that to this change? > > Fixes: 3d82904559f4 ("usb: cdnsp: cdns3 Add main part of Cadence USBSSP DRD Driver") > cc: stable@vger.kernel.org > Signed-off-by: Pawel Laszczak <pawell@cadence.com> > --- > drivers/usb/cdns3/cdnsp-gadget.c | 22 ++++++++++++++++++++++ > drivers/usb/cdns3/cdnsp-gadget.h | 4 ++++ > 2 files changed, 26 insertions(+) > > diff --git a/drivers/usb/cdns3/cdnsp-gadget.c b/drivers/usb/cdns3/cdnsp-gadget.c > index 87f310841735..b12581b94567 100644 > --- a/drivers/usb/cdns3/cdnsp-gadget.c > +++ b/drivers/usb/cdns3/cdnsp-gadget.c > @@ -139,6 +139,21 @@ static void cdnsp_clear_port_change_bit(struct cdnsp_device *pdev, > (portsc & PORT_CHANGE_BITS), port_regs); > } > > +static void cdnsp_set_apb_timeout_value(struct cdnsp_device *pdev) > +{ > + __le32 __iomem *reg; > + void __iomem *base; > + u32 offset = 0; > + u32 val; > + > + base = &pdev->cap_regs->hc_capbase; > + offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP); > + reg = base + offset + REG_CHICKEN_BITS_3_OFFSET; > + > + val = le32_to_cpu(readl(reg)); > + writel(cpu_to_le32(CHICKEN_APB_TIMEOUT_SET(val)), reg); Do you need to do a read to ensure that the write is flushed to the device before continuing? > +} > + > static void cdnsp_set_chicken_bits_2(struct cdnsp_device *pdev, u32 bit) > { > __le32 __iomem *reg; > @@ -1798,6 +1813,13 @@ static int cdnsp_gen_setup(struct cdnsp_device *pdev) > pdev->hci_version = HC_VERSION(pdev->hcc_params); > pdev->hcc_params = readl(&pdev->cap_regs->hcc_params); > > + /* In very rare cases after resuming controller from L1 to L0 it reads > + * registers before the clock has been enabled and as the result driver > + * reads incorrect value. > + * To fix this issue driver increases APB timeout value. > + */ Nit, please use the "normal" kernel comment style. thanks, greg k-h
On 25-04-10 07:34:16, Pawel Laszczak wrote: > Subject: [PATCH] usb: cdnsp: Fix issue with resuming from L1 > > In very rare cases after resuming controller from L1 to L0 it reads > registers before the clock has been enabled and as the result driver > reads incorrect value. > To fix this issue driver increases APB timeout value. L1 is the link state during the runtime, usually, we do not disable APB clock at runtime since SW may access registers. Would you please explain more about this scenario? Besides, why only device mode needs it? Peter > > Probably this issue occurs only on Cadence platform but fix > should have no impact for other existing platforms. > > Fixes: 3d82904559f4 ("usb: cdnsp: cdns3 Add main part of Cadence USBSSP DRD Driver") > cc: stable@vger.kernel.org > Signed-off-by: Pawel Laszczak <pawell@cadence.com> > --- > drivers/usb/cdns3/cdnsp-gadget.c | 22 ++++++++++++++++++++++ > drivers/usb/cdns3/cdnsp-gadget.h | 4 ++++ > 2 files changed, 26 insertions(+) > > diff --git a/drivers/usb/cdns3/cdnsp-gadget.c b/drivers/usb/cdns3/cdnsp-gadget.c > index 87f310841735..b12581b94567 100644 > --- a/drivers/usb/cdns3/cdnsp-gadget.c > +++ b/drivers/usb/cdns3/cdnsp-gadget.c > @@ -139,6 +139,21 @@ static void cdnsp_clear_port_change_bit(struct cdnsp_device *pdev, > (portsc & PORT_CHANGE_BITS), port_regs); > } > > +static void cdnsp_set_apb_timeout_value(struct cdnsp_device *pdev) > +{ > + __le32 __iomem *reg; > + void __iomem *base; > + u32 offset = 0; > + u32 val; > + > + base = &pdev->cap_regs->hc_capbase; > + offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP); > + reg = base + offset + REG_CHICKEN_BITS_3_OFFSET; > + > + val = le32_to_cpu(readl(reg)); > + writel(cpu_to_le32(CHICKEN_APB_TIMEOUT_SET(val)), reg); > +} > + > static void cdnsp_set_chicken_bits_2(struct cdnsp_device *pdev, u32 bit) > { > __le32 __iomem *reg; > @@ -1798,6 +1813,13 @@ static int cdnsp_gen_setup(struct cdnsp_device *pdev) > pdev->hci_version = HC_VERSION(pdev->hcc_params); > pdev->hcc_params = readl(&pdev->cap_regs->hcc_params); > > + /* In very rare cases after resuming controller from L1 to L0 it reads > + * registers before the clock has been enabled and as the result driver > + * reads incorrect value. > + * To fix this issue driver increases APB timeout value. > + */ > + cdnsp_set_apb_timeout_value(pdev); > + > cdnsp_get_rev_cap(pdev); > > /* Make sure the Device Controller is halted. */ > diff --git a/drivers/usb/cdns3/cdnsp-gadget.h b/drivers/usb/cdns3/cdnsp-gadget.h > index 84887dfea763..a4d678fba005 100644 > --- a/drivers/usb/cdns3/cdnsp-gadget.h > +++ b/drivers/usb/cdns3/cdnsp-gadget.h > @@ -520,6 +520,10 @@ struct cdnsp_rev_cap { > #define REG_CHICKEN_BITS_2_OFFSET 0x48 > #define CHICKEN_XDMA_2_TP_CACHE_DIS BIT(28) > > +#define REG_CHICKEN_BITS_3_OFFSET 0x4C > +#define CHICKEN_APB_TIMEOUT_VALUE 0x1C20 > +#define CHICKEN_APB_TIMEOUT_SET(p) (((p) & ~GENMASK(21, 0)) | CHICKEN_APB_TIMEOUT_VALUE) > + > /* XBUF Extended Capability ID. */ > #define XBUF_CAP_ID 0xCB > #define XBUF_RX_TAG_MASK_0_OFFSET 0x1C > -- > 2.43.0 >
> > >On Thu, Apr 10, 2025 at 07:34:16AM +0000, Pawel Laszczak wrote: >> Subject: [PATCH] usb: cdnsp: Fix issue with resuming from L1 > >Why is the subject line duplicated here? Can you fix up your git send-email >process to not do that? > >> In very rare cases after resuming controller from L1 to L0 it reads >> registers before the clock has been enabled and as the result driver >> reads incorrect value. >> To fix this issue driver increases APB timeout value. >> >> Probably this issue occurs only on Cadence platform but fix should >> have no impact for other existing platforms. > >If this is the case, shouldn't you just handle this for Cadence-specific hardware >and add the check for that to this change? This fix will not have negative impact for other platforms, but I'm not sure whether other platforms are free from this issue. It is very hard to recreate and debug this issue. Thanks, Pawel > >> >> Fixes: 3d82904559f4 ("usb: cdnsp: cdns3 Add main part of Cadence >> USBSSP DRD Driver") >> cc: stable@vger.kernel.org >> Signed-off-by: Pawel Laszczak <pawell@cadence.com> >> --- >> drivers/usb/cdns3/cdnsp-gadget.c | 22 ++++++++++++++++++++++ >> drivers/usb/cdns3/cdnsp-gadget.h | 4 ++++ >> 2 files changed, 26 insertions(+) >> >> diff --git a/drivers/usb/cdns3/cdnsp-gadget.c >> b/drivers/usb/cdns3/cdnsp-gadget.c >> index 87f310841735..b12581b94567 100644 >> --- a/drivers/usb/cdns3/cdnsp-gadget.c >> +++ b/drivers/usb/cdns3/cdnsp-gadget.c >> @@ -139,6 +139,21 @@ static void cdnsp_clear_port_change_bit(struct >cdnsp_device *pdev, >> (portsc & PORT_CHANGE_BITS), port_regs); } >> >> +static void cdnsp_set_apb_timeout_value(struct cdnsp_device *pdev) { >> + __le32 __iomem *reg; >> + void __iomem *base; >> + u32 offset = 0; >> + u32 val; >> + >> + base = &pdev->cap_regs->hc_capbase; >> + offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP); >> + reg = base + offset + REG_CHICKEN_BITS_3_OFFSET; >> + >> + val = le32_to_cpu(readl(reg)); >> + writel(cpu_to_le32(CHICKEN_APB_TIMEOUT_SET(val)), reg); > >Do you need to do a read to ensure that the write is flushed to the device before >continuing? > >> +} >> + >> static void cdnsp_set_chicken_bits_2(struct cdnsp_device *pdev, u32 >> bit) { >> __le32 __iomem *reg; >> @@ -1798,6 +1813,13 @@ static int cdnsp_gen_setup(struct cdnsp_device >*pdev) >> pdev->hci_version = HC_VERSION(pdev->hcc_params); >> pdev->hcc_params = readl(&pdev->cap_regs->hcc_params); >> >> + /* In very rare cases after resuming controller from L1 to L0 it reads >> + * registers before the clock has been enabled and as the result driver >> + * reads incorrect value. >> + * To fix this issue driver increases APB timeout value. >> + */ > >Nit, please use the "normal" kernel comment style. > >thanks, > >greg k-h
>-----Original Message----- >From: Pawel Laszczak >Sent: Friday, April 11, 2025 11:40 AM >To: gregkh@linuxfoundation.org >Cc: peter.chen@kernel.org; linux-usb@vger.kernel.org; linux- >kernel@vger.kernel.org; stable@vger.kernel.org >Subject: RE: [PATCH] usb: cdnsp: Fix issue with resuming from L1 > >> >> >>On Thu, Apr 10, 2025 at 07:34:16AM +0000, Pawel Laszczak wrote: >>> Subject: [PATCH] usb: cdnsp: Fix issue with resuming from L1 >> >>Why is the subject line duplicated here? Can you fix up your git >>send-email process to not do that? >> >>> In very rare cases after resuming controller from L1 to L0 it reads >>> registers before the clock has been enabled and as the result driver >>> reads incorrect value. >>> To fix this issue driver increases APB timeout value. >>> >>> Probably this issue occurs only on Cadence platform but fix should >>> have no impact for other existing platforms. >> >>If this is the case, shouldn't you just handle this for >>Cadence-specific hardware and add the check for that to this change? > >This fix will not have negative impact for other platforms, but I'm not sure >whether other platforms are free from this issue. >It is very hard to recreate and debug this issue. Sorry, you have right should be platform specific. Other platform with Cadence USB controller may require this time even longer. > >Thanks, >Pawel >> >>> >>> Fixes: 3d82904559f4 ("usb: cdnsp: cdns3 Add main part of Cadence >>> USBSSP DRD Driver") >>> cc: stable@vger.kernel.org >>> Signed-off-by: Pawel Laszczak <pawell@cadence.com> >>> --- >>> drivers/usb/cdns3/cdnsp-gadget.c | 22 ++++++++++++++++++++++ >>> drivers/usb/cdns3/cdnsp-gadget.h | 4 ++++ >>> 2 files changed, 26 insertions(+) >>> >>> diff --git a/drivers/usb/cdns3/cdnsp-gadget.c >>> b/drivers/usb/cdns3/cdnsp-gadget.c >>> index 87f310841735..b12581b94567 100644 >>> --- a/drivers/usb/cdns3/cdnsp-gadget.c >>> +++ b/drivers/usb/cdns3/cdnsp-gadget.c >>> @@ -139,6 +139,21 @@ static void cdnsp_clear_port_change_bit(struct >>cdnsp_device *pdev, >>> (portsc & PORT_CHANGE_BITS), port_regs); } >>> >>> +static void cdnsp_set_apb_timeout_value(struct cdnsp_device *pdev) { >>> + __le32 __iomem *reg; >>> + void __iomem *base; >>> + u32 offset = 0; >>> + u32 val; >>> + >>> + base = &pdev->cap_regs->hc_capbase; >>> + offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP); >>> + reg = base + offset + REG_CHICKEN_BITS_3_OFFSET; >>> + >>> + val = le32_to_cpu(readl(reg)); >>> + writel(cpu_to_le32(CHICKEN_APB_TIMEOUT_SET(val)), reg); >> >>Do you need to do a read to ensure that the write is flushed to the >>device before continuing? >> >>> +} >>> + >>> static void cdnsp_set_chicken_bits_2(struct cdnsp_device *pdev, u32 >>> bit) { >>> __le32 __iomem *reg; >>> @@ -1798,6 +1813,13 @@ static int cdnsp_gen_setup(struct cdnsp_device >>*pdev) >>> pdev->hci_version = HC_VERSION(pdev->hcc_params); >>> pdev->hcc_params = readl(&pdev->cap_regs->hcc_params); >>> >>> + /* In very rare cases after resuming controller from L1 to L0 it reads >>> + * registers before the clock has been enabled and as the result driver >>> + * reads incorrect value. >>> + * To fix this issue driver increases APB timeout value. >>> + */ >> >>Nit, please use the "normal" kernel comment style. >> >>thanks, >> >>greg k-h
> > >On 25-04-10 07:34:16, Pawel Laszczak wrote: >> Subject: [PATCH] usb: cdnsp: Fix issue with resuming from L1 >> >> In very rare cases after resuming controller from L1 to L0 it reads >> registers before the clock has been enabled and as the result driver >> reads incorrect value. >> To fix this issue driver increases APB timeout value. > >L1 is the link state during the runtime, usually, we do not disable APB clock at >runtime since SW may access registers. Would you please explain more about >this scenario? Sorry, I'm not a hardware guy and I misunderstood the root cause of the problem. Description of patch is incorrect. System uses several clock domains. When controller goes to L1 the UTMI clock can be disabled. Most registers are in APB domain, but some are on UTMI domain (e.g PORTSC). During transition L1 -> L0 driver try to read PORTSC in interrupt runtime and read 0xFFFFFF because it receives timeout on APB (APB clock is enabled). When controller try to read PORTSC controller synchronize two clock domains, but UTMI has still disabled clock. It's the reason why APB gets timeout error and read 0xFFFFFF. Increasing APB timeout value gives controller more time to enable UTMI clock and synchronize domain. This issue occurs one per 30 - 500 minutes in case in which I added some Extra delay between some requests to force the massive LPM transaction. Time is hardware/platform specific and should be parameterized for the platform. Patch will be improved. Thanks, Pawel > >Besides, why only device mode needs it? We haven't observed this issue on host side. > >Peter >> >> Probably this issue occurs only on Cadence platform but fix should >> have no impact for other existing platforms. >> >> Fixes: 3d82904559f4 ("usb: cdnsp: cdns3 Add main part of Cadence >> USBSSP DRD Driver") >> cc: stable@vger.kernel.org >> Signed-off-by: Pawel Laszczak <pawell@cadence.com> >> --- >> drivers/usb/cdns3/cdnsp-gadget.c | 22 ++++++++++++++++++++++ >> drivers/usb/cdns3/cdnsp-gadget.h | 4 ++++ >> 2 files changed, 26 insertions(+) >> >> diff --git a/drivers/usb/cdns3/cdnsp-gadget.c >> b/drivers/usb/cdns3/cdnsp-gadget.c >> index 87f310841735..b12581b94567 100644 >> --- a/drivers/usb/cdns3/cdnsp-gadget.c >> +++ b/drivers/usb/cdns3/cdnsp-gadget.c >> @@ -139,6 +139,21 @@ static void cdnsp_clear_port_change_bit(struct >cdnsp_device *pdev, >> (portsc & PORT_CHANGE_BITS), port_regs); } >> >> +static void cdnsp_set_apb_timeout_value(struct cdnsp_device *pdev) { >> + __le32 __iomem *reg; >> + void __iomem *base; >> + u32 offset = 0; >> + u32 val; >> + >> + base = &pdev->cap_regs->hc_capbase; >> + offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP); >> + reg = base + offset + REG_CHICKEN_BITS_3_OFFSET; >> + >> + val = le32_to_cpu(readl(reg)); >> + writel(cpu_to_le32(CHICKEN_APB_TIMEOUT_SET(val)), reg); } >> + >> static void cdnsp_set_chicken_bits_2(struct cdnsp_device *pdev, u32 >> bit) { >> __le32 __iomem *reg; >> @@ -1798,6 +1813,13 @@ static int cdnsp_gen_setup(struct cdnsp_device >*pdev) >> pdev->hci_version = HC_VERSION(pdev->hcc_params); >> pdev->hcc_params = readl(&pdev->cap_regs->hcc_params); >> >> + /* In very rare cases after resuming controller from L1 to L0 it reads >> + * registers before the clock has been enabled and as the result driver >> + * reads incorrect value. >> + * To fix this issue driver increases APB timeout value. >> + */ >> + cdnsp_set_apb_timeout_value(pdev); >> + >> cdnsp_get_rev_cap(pdev); >> >> /* Make sure the Device Controller is halted. */ diff --git >> a/drivers/usb/cdns3/cdnsp-gadget.h b/drivers/usb/cdns3/cdnsp-gadget.h >> index 84887dfea763..a4d678fba005 100644 >> --- a/drivers/usb/cdns3/cdnsp-gadget.h >> +++ b/drivers/usb/cdns3/cdnsp-gadget.h >> @@ -520,6 +520,10 @@ struct cdnsp_rev_cap { >> #define REG_CHICKEN_BITS_2_OFFSET 0x48 >> #define CHICKEN_XDMA_2_TP_CACHE_DIS BIT(28) >> >> +#define REG_CHICKEN_BITS_3_OFFSET 0x4C >> +#define CHICKEN_APB_TIMEOUT_VALUE 0x1C20 >> +#define CHICKEN_APB_TIMEOUT_SET(p) (((p) & ~GENMASK(21, 0)) | >> +CHICKEN_APB_TIMEOUT_VALUE) >> + >> /* XBUF Extended Capability ID. */ >> #define XBUF_CAP_ID 0xCB >> #define XBUF_RX_TAG_MASK_0_OFFSET 0x1C >> -- >> 2.43.0 >> > >-- > >Best regards, >Peter
diff --git a/drivers/usb/cdns3/cdnsp-gadget.c b/drivers/usb/cdns3/cdnsp-gadget.c index 87f310841735..b12581b94567 100644 --- a/drivers/usb/cdns3/cdnsp-gadget.c +++ b/drivers/usb/cdns3/cdnsp-gadget.c @@ -139,6 +139,21 @@ static void cdnsp_clear_port_change_bit(struct cdnsp_device *pdev, (portsc & PORT_CHANGE_BITS), port_regs); } +static void cdnsp_set_apb_timeout_value(struct cdnsp_device *pdev) +{ + __le32 __iomem *reg; + void __iomem *base; + u32 offset = 0; + u32 val; + + base = &pdev->cap_regs->hc_capbase; + offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP); + reg = base + offset + REG_CHICKEN_BITS_3_OFFSET; + + val = le32_to_cpu(readl(reg)); + writel(cpu_to_le32(CHICKEN_APB_TIMEOUT_SET(val)), reg); +} + static void cdnsp_set_chicken_bits_2(struct cdnsp_device *pdev, u32 bit) { __le32 __iomem *reg; @@ -1798,6 +1813,13 @@ static int cdnsp_gen_setup(struct cdnsp_device *pdev) pdev->hci_version = HC_VERSION(pdev->hcc_params); pdev->hcc_params = readl(&pdev->cap_regs->hcc_params); + /* In very rare cases after resuming controller from L1 to L0 it reads + * registers before the clock has been enabled and as the result driver + * reads incorrect value. + * To fix this issue driver increases APB timeout value. + */ + cdnsp_set_apb_timeout_value(pdev); + cdnsp_get_rev_cap(pdev); /* Make sure the Device Controller is halted. */ diff --git a/drivers/usb/cdns3/cdnsp-gadget.h b/drivers/usb/cdns3/cdnsp-gadget.h index 84887dfea763..a4d678fba005 100644 --- a/drivers/usb/cdns3/cdnsp-gadget.h +++ b/drivers/usb/cdns3/cdnsp-gadget.h @@ -520,6 +520,10 @@ struct cdnsp_rev_cap { #define REG_CHICKEN_BITS_2_OFFSET 0x48 #define CHICKEN_XDMA_2_TP_CACHE_DIS BIT(28) +#define REG_CHICKEN_BITS_3_OFFSET 0x4C +#define CHICKEN_APB_TIMEOUT_VALUE 0x1C20 +#define CHICKEN_APB_TIMEOUT_SET(p) (((p) & ~GENMASK(21, 0)) | CHICKEN_APB_TIMEOUT_VALUE) + /* XBUF Extended Capability ID. */ #define XBUF_CAP_ID 0xCB #define XBUF_RX_TAG_MASK_0_OFFSET 0x1C
Subject: [PATCH] usb: cdnsp: Fix issue with resuming from L1 In very rare cases after resuming controller from L1 to L0 it reads registers before the clock has been enabled and as the result driver reads incorrect value. To fix this issue driver increases APB timeout value. Probably this issue occurs only on Cadence platform but fix should have no impact for other existing platforms. Fixes: 3d82904559f4 ("usb: cdnsp: cdns3 Add main part of Cadence USBSSP DRD Driver") cc: stable@vger.kernel.org Signed-off-by: Pawel Laszczak <pawell@cadence.com> --- drivers/usb/cdns3/cdnsp-gadget.c | 22 ++++++++++++++++++++++ drivers/usb/cdns3/cdnsp-gadget.h | 4 ++++ 2 files changed, 26 insertions(+)