From patchwork Wed Oct 14 13:19:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11837651 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09955921 for ; Wed, 14 Oct 2020 13:19:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D47CF22201 for ; Wed, 14 Oct 2020 13:19:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="KrFUI0fQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728844AbgJNNTs (ORCPT ); Wed, 14 Oct 2020 09:19:48 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:53256 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727721AbgJNNTq (ORCPT ); Wed, 14 Oct 2020 09:19:46 -0400 X-UUID: f39527c9ff35424a91fa20feeb0c18f8-20201014 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=VKbmk+q6TZp792M8YotOsz2Eix0rdiCGpnXktYfljzs=; b=KrFUI0fQZnYCJsT9rj2/FfJyHQk9IkMhm7ou2yfCkDe0MhvapxojZ0RgDvyIanOxFS9DVw4x/TZYiaq5drMYWNNOHzNgADWaG35JN/fCKOEQJ9CajopXaDkiKnMsKDxIRz5Yp2ty0pD6pEZvu5ckqNHNX8EMOZt6FFLaJLVhm9I=; X-UUID: f39527c9ff35424a91fa20feeb0c18f8-20201014 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1533085728; Wed, 14 Oct 2020 21:19:41 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Oct 2020 21:19:38 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 21:19:37 +0800 From: Crystal Guo To: , , , CC: , , , , , Subject: [v6,0/4] watchdog: mt8192: add wdt support Date: Wed, 14 Oct 2020 21:19:32 +0800 Message-ID: <20201014131936.20584-1-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: AACF75C595E88535A25ED18B74F5FCCC1B0D61D4691CD1ADFFED2FA5B29200222000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This patches aim to add watchdog support for MT8192. change in v6: 1. add change log. 2. remove Reviewed-by tag on[v5,2/4] change in v5: fix typos on mt8192-reset.h (https://patchwork.kernel.org/patch/11697493/) change in v4: just revise v3 commit messages. [v4,1/5] fix the description of compatible is Reviewed-by: Matthias and Guenter. [v4,2/5] update watchdog device node for mt8183 is Acked-by: Guenter, and will be applied to v5.9-next/dts64. [v4,4/5] add toprgu reset-controller head file for MT8192 platform is Reviewed-by: Matthias, and Acked-by: Guenter. [v4,5/5] add support for watchdog device found in MT8192 SoC is Reviewed-by: Matthias and Guenter. change in v3: 1. separate [v2,1/3] to fix the original mt2712 and mt8183 compatibles and add new board as: [v3,1/5] fix mt2712 and mt8183 description of compatible, since mt2712 and mt8183 also provide sub-system software reset features, but mt6589 not support this feature. (Reviewed-by: Matthias) [v3,2/5] update watchdog device node for mt8183 [v3,3/5] update mtk-wdt document for MT8192 platform 2. [v3, 4/5] is same as [v2,2/3] (Reviewed-by: Matthias) 3. modify the commit message of [v2,3/3] [v3,5/5] add support for watchdog device found in MT8192 SoC(Reviewed-by: Matthias and Guenter) v2 changes: Abandon V1 changes,and add the following changes: [v2,1/3] update mtk-wdt document for mt2712, mt8183 and mt8192. [v2,2/3] add toprgu reset-controller head file for MT8192 platform (Reviewed-by: Matthias) [v2,3/3] add support for watchdog device found in MT8192 SoC( Reviewed-by: Matthias) v1 changes: Instead of submit the mt8192-reset.h, get the number of reset bits from dtsi directly. Crystal Guo (4): dt-binding: mediatek: watchdog: fix the description of compatible dt-binding: mediatek: mt8192: update mtk-wdt document dt-binding: mt8192: add toprgu reset-controller head file watchdog: mt8192: add wdt support .../devicetree/bindings/watchdog/mtk-wdt.txt | 5 ++-- drivers/watchdog/mtk_wdt.c | 6 ++++ .../reset-controller/mt8192-resets.h | 30 +++++++++++++++++++ 3 files changed, 39 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h