From patchwork Tue Jul 28 10:42:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11688899 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0675F138C for ; Tue, 28 Jul 2020 10:43:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E2B90207E8 for ; Tue, 28 Jul 2020 10:43:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="L08uOlwa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728699AbgG1KnW (ORCPT ); Tue, 28 Jul 2020 06:43:22 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:18882 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728686AbgG1KnW (ORCPT ); Tue, 28 Jul 2020 06:43:22 -0400 X-UUID: e08ada8fc8f847769d1a5a75c59385a6-20200728 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=fGh635YPSKDx8TpTukFSxvqdKrdqDpycLk2vh1BFhDc=; b=L08uOlwa8o0OzVxkLlQNxVJCWRJ/nuGiMBlG0ISqkQ1S/9aaI3tqoqJdaOtkCQCRHC5/nyY2ay8Oj0ODUVN5D/PT5k/swk659JtO7TY+GYUc5ySgZaRXNrXaVaXFu+Ijr/V3a0+bI7X+LTJ3i7B0WmZVcy87hZbNWEPC1wHn0rI=; X-UUID: e08ada8fc8f847769d1a5a75c59385a6-20200728 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2144090476; Tue, 28 Jul 2020 18:43:18 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 28 Jul 2020 18:43:16 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 28 Jul 2020 18:43:14 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [PATCH 1/3] watchdog: mtk_wdt: remove mt8xxx-resets.h Date: Tue, 28 Jul 2020 18:42:27 +0800 Message-ID: <1595932949-7033-1-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-TM-SNTS-SMTP: 71B9F2D85162E9CD930E185F74479062C12A56CDD28885323C9E66983C5603302000:8 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org mt8xxx-resets.h actually just used to define TOPRGU_SW_RST_NUM. Instead of resubmit the mt8xxx-reset.h for a new IC, get the number of reset bits from dtsi is more easier to maintain. Signed-off-by: Crystal Guo --- drivers/watchdog/mtk_wdt.c | 26 +++++--------------------- 1 file changed, 5 insertions(+), 21 deletions(-) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393..adc88c2 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -9,8 +9,6 @@ * Based on sunxi_wdt.c */ -#include -#include #include #include #include @@ -64,18 +62,6 @@ struct mtk_wdt_dev { struct reset_controller_dev rcdev; }; -struct mtk_wdt_data { - int toprgu_sw_rst_num; -}; - -static const struct mtk_wdt_data mt2712_data = { - .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, -}; - -static const struct mtk_wdt_data mt8183_data = { - .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, -}; - static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -248,7 +234,7 @@ static int mtk_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_wdt_dev *mtk_wdt; - const struct mtk_wdt_data *wdt_data; + u32 toprgu_sw_rst_num; int err; mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); @@ -284,10 +270,10 @@ static int mtk_wdt_probe(struct platform_device *pdev) dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", mtk_wdt->wdt_dev.timeout, nowayout); - wdt_data = of_device_get_match_data(dev); - if (wdt_data) { - err = toprgu_register_reset_controller(pdev, - wdt_data->toprgu_sw_rst_num); + err = of_property_read_u32(pdev->dev.of_node, "rst-num", + &toprgu_sw_rst_num); + if (!err) { + err = toprgu_register_reset_controller(pdev, toprgu_sw_rst_num); if (err) return err; } @@ -319,9 +305,7 @@ static int mtk_wdt_resume(struct device *dev) #endif static const struct of_device_id mtk_wdt_dt_ids[] = { - { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, - { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);