From patchwork Wed Jul 29 10:02:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11690721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8466314B7 for ; Wed, 29 Jul 2020 10:02:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D3EE2075D for ; Wed, 29 Jul 2020 10:02:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="UotqtxYZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726664AbgG2KCk (ORCPT ); Wed, 29 Jul 2020 06:02:40 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:52293 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726645AbgG2KCg (ORCPT ); Wed, 29 Jul 2020 06:02:36 -0400 X-UUID: 6792aa04c7e14555b13847bce6b20a09-20200729 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=vh67dDG+PPF5w/5q7NusigBDM+ZZIr+ZRqBQV1zStds=; b=UotqtxYZ19vdsC5qy2/SGNztYUUbhjAeJNhEGKQNZKmg823MAXWHucEIrS4oHBph7Ogg5++8MRwpXlpu05fOezRRdhmvGjBOpL/aUkQGGhraSIQ+/PNPuj/0Wc3ETWHUkdAtbmVa8oUbfmTVg9DtEzakujKr3h6efB3uQy8hss4=; X-UUID: 6792aa04c7e14555b13847bce6b20a09-20200729 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2119183333; Wed, 29 Jul 2020 18:02:32 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 18:02:29 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 29 Jul 2020 18:02:29 +0800 From: Crystal Guo To: , , CC: , , , , , , , Crystal Guo Subject: [v2,3/3] watchdog: mt8192: add wdt support Date: Wed, 29 Jul 2020 18:02:02 +0800 Message-ID: <1596016922-13184-4-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596016922-13184-1-git-send-email-crystal.guo@mediatek.com> References: <1596016922-13184-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org add driver setting to support mt8192 wdt Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393..aef0c2d 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -76,6 +77,10 @@ struct mtk_wdt_data { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt8192_data = { + .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, +}; + static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -322,6 +327,7 @@ static int mtk_wdt_resume(struct device *dev) { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);