From patchwork Thu Jul 30 10:21:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11692737 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BD4F13B6 for ; Thu, 30 Jul 2020 10:22:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75E922083B for ; Thu, 30 Jul 2020 10:22:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="AnCLwfNR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729140AbgG3KWj (ORCPT ); Thu, 30 Jul 2020 06:22:39 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:34215 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728972AbgG3KW2 (ORCPT ); Thu, 30 Jul 2020 06:22:28 -0400 X-UUID: 9506b8dc5a2442229bffa56ed4d0c835-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=650NVCPZG1KcydX0hTrnKCdiU0nIw3CgigzQoQXdQQk=; b=AnCLwfNRoY0Za/crMZD+KmDbN9m1OhpBK3T4QnCwpTA+Fz6xaizLnA8+Bsri4uF3GYNldQEECciG96dspMNWxteHicn2/O+UikznD446kZTC1aOWaHhyo3cENUvchTpwDeFmYBPKVuUM/nCwDrGjO5z9AFNxZ07AcWHbZkKJLmY=; X-UUID: 9506b8dc5a2442229bffa56ed4d0c835-20200730 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1624301822; Thu, 30 Jul 2020 18:22:23 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 18:22:19 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 18:22:19 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v3,4/5] dt-binding: mt8192: add toprgu reset-controller head file Date: Thu, 30 Jul 2020 18:21:49 +0800 Message-ID: <1596104510-11113-5-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> References: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org add toprgu reset-controller head file for MT8192 platform Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger --- .../dt-bindings/reset-controller/mt8192-resets.h | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h new file mode 100644 index 0000000..84fee34 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8192-resets.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */