From patchwork Thu Jul 23 09:07:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 11680485 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 73C2D13B6 for ; Thu, 23 Jul 2020 09:08:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 519A620714 for ; Thu, 23 Jul 2020 09:08:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="VLcdCslJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726303AbgGWJIf (ORCPT ); Thu, 23 Jul 2020 05:08:35 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:63505 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726127AbgGWJIe (ORCPT ); Thu, 23 Jul 2020 05:08:34 -0400 X-UUID: 57ce595b17674c7ea05b1e91a51ef1f1-20200723 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VUimYVBdlfMRsNpI/7dqGrtRjsY9u4/ZFKxfCAFSY+w=; b=VLcdCslJXi5AC6hQ6vfWMY7oMwr56EOHEwu7Yt6hvrDSu331yTDS9RYLpc/XnNxs0GZHLe20+Jt3O6VaMYCtwoeb9MjmWXGUHNPeXHYZ0fhWZL/hXzwp4fUzbyhbjIZ2chru6jidg7j2/dVa/bZoqUPlhzcPbApIEYAhnNPJeMs=; X-UUID: 57ce595b17674c7ea05b1e91a51ef1f1-20200723 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1658060345; Thu, 23 Jul 2020 17:08:30 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 23 Jul 2020 17:08:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 23 Jul 2020 17:08:28 +0800 From: Seiya Wang To: Greg Kroah-Hartman , Rob Herring , Matthias Brugger , Wim Van Sebroeck , Guenter Roeck CC: , , , , , , , Seiya Wang Subject: [PATCH 2/4] dt-bindings: serial: Add compatible for Mediatek MT8192 Date: Thu, 23 Jul 2020 17:07:29 +0800 Message-ID: <20200723090731.4482-3-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200723090731.4482-1-seiya.wang@mediatek.com> References: <20200723090731.4482-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This commit adds dt-binding documentation of uart for Mediatek MT8192 SoC Platform. Signed-off-by: Seiya Wang Acked-by: Rob Herring --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 3a3b57079f0d..647b5aee86f3 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -19,6 +19,7 @@ Required properties: * "mediatek,mt8135-uart" for MT8135 compatible UARTS * "mediatek,mt8173-uart" for MT8173 compatible UARTS * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS + * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS * "mediatek,mt8516-uart" for MT8516 compatible UARTS * "mediatek,mt6577-uart" for MT6577 and all of the above