From patchwork Thu Jul 23 09:07:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 11680489 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF3866C1 for ; Thu, 23 Jul 2020 09:08:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C290122CB3 for ; Thu, 23 Jul 2020 09:08:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="hasDjezS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728175AbgGWJIi (ORCPT ); Thu, 23 Jul 2020 05:08:38 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:54423 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726127AbgGWJIh (ORCPT ); Thu, 23 Jul 2020 05:08:37 -0400 X-UUID: 996cd9ff55234ef9a6b6ba5f2e0742cf-20200723 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=E28fbb5ne1MmlUXosoO8B39FMtBz2eDLvLgvsB/y8Gg=; b=hasDjezS+1moNcJDTn/jBBtVZgiYCJxlAZGCeQ4rJT8372DbcXUdIAaNe0IaMkv1SwN+gmgtQpkVLEPVwkA31/MljtlVMilGhx1JveTs9Z2KROoTumEIGKYksp/pQHz35qYYNVS9SGMRTrOkXCmFFfT1kyja8J4Jpo1+pj4r6ro=; X-UUID: 996cd9ff55234ef9a6b6ba5f2e0742cf-20200723 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 291139438; Thu, 23 Jul 2020 17:08:34 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 23 Jul 2020 17:08:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 23 Jul 2020 17:08:32 +0800 From: Seiya Wang To: Greg Kroah-Hartman , Rob Herring , Matthias Brugger , Wim Van Sebroeck , Guenter Roeck CC: , , , , , , , Crystal Guo Subject: [PATCH 3/4] watchdog: mt8192: add wdt support Date: Thu, 23 Jul 2020 17:07:30 +0800 Message-ID: <20200723090731.4482-4-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200723090731.4482-1-seiya.wang@mediatek.com> References: <20200723090731.4482-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org From: Crystal Guo add driver setting to support mt8192 wdt Signed-off-by: Crystal Guo --- drivers/watchdog/mtk_wdt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393f609d..ad23596170af 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -76,6 +76,10 @@ static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt8192_data = { + .toprgu_sw_rst_num = 23, +}; + static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -322,6 +326,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);