From patchwork Mon Aug 3 07:15:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11697479 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57F4F138A for ; Mon, 3 Aug 2020 07:16:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4000B206E9 for ; Mon, 3 Aug 2020 07:16:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="M0gif7lQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726243AbgHCHQA (ORCPT ); Mon, 3 Aug 2020 03:16:00 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:39511 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726125AbgHCHPz (ORCPT ); Mon, 3 Aug 2020 03:15:55 -0400 X-UUID: da9ff929f236497985a6641e3534a480-20200803 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CNroCAZ0RL2N4ZfavyHWU/kNJ5us1mqnMHLPTgRxTSI=; b=M0gif7lQTTZI2Kps5e9YXK+h5ChG3QBhzNG+n2X8uOG/5ggKCkI40KJ3gcXGaae+25iZyevPHqkTXF+nVNsD2m7ktid1gZ1vqbzkzH6uJ8woUO9hIi0RoY05WWU3TeXQw8a4Qd6ZIpYUaFmiiPCXA1JRuMypvZR2cIBIx7W3d6c=; X-UUID: da9ff929f236497985a6641e3534a480-20200803 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1374218471; Mon, 03 Aug 2020 15:15:51 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 Aug 2020 15:15:47 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 Aug 2020 15:15:47 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v4,4/5] dt-binding: mt8192: add toprgu reset-controller head file Date: Mon, 3 Aug 2020 15:15:00 +0800 Message-ID: <20200803071501.30634-5-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200803071501.30634-1-crystal.guo@mediatek.com> References: <20200803071501.30634-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: CC8ACE99E7C3A2203BB499DE3F720B05598A06C197EC599126E29BFB8327004D2000:8 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org add toprgu reset-controller head file for MT8192 platform Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Acked-by: Guenter Roeck --- .../reset-controller/mt8192-resets.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h new file mode 100644 index 000000000000..84fee34f1c32 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8192-resets.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */