From patchwork Fri Aug 28 13:05:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11742755 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 152FB17CF for ; Fri, 28 Aug 2020 13:10:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ECE1420825 for ; Fri, 28 Aug 2020 13:10:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729574AbgH1NKL (ORCPT ); Fri, 28 Aug 2020 09:10:11 -0400 Received: from foss.arm.com ([217.140.110.172]:48820 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729429AbgH1NHh (ORCPT ); Fri, 28 Aug 2020 09:07:37 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C0B8713A1; Fri, 28 Aug 2020 06:06:21 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8D1C33F66B; Fri, 28 Aug 2020 06:06:20 -0700 (PDT) From: Andre Przywara To: Rob Herring , devicetree@vger.kernel.org Cc: Guenter Roeck , Wim Van Sebroeck , Viresh Kumar , linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Chanho Min Subject: [PATCH 06/10] arm64: dts: lg: Fix SP805 clocks Date: Fri, 28 Aug 2020 14:05:58 +0100 Message-Id: <20200828130602.42203-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200828130602.42203-1-andre.przywara@arm.com> References: <20200828130602.42203-1-andre.przywara@arm.com> Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The SP805 DT binding requires two clocks to be specified, but the two LG platform DTs currently only specify one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux (and U-Boot) SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/lg/lg1312.dtsi | 4 ++-- arch/arm64/boot/dts/lg/lg1313.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index e2a1564597c8..081fe7a9f605 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -141,8 +141,8 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xfd200000 0x1000>; interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "wdog_clk", "apb_pclk"; }; uart0: serial@fe000000 { compatible = "arm,pl011", "arm,primecell"; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index a54d14d7ae6f..604bb6975337 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -141,8 +141,8 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xfd200000 0x1000>; interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "wdog_clk", "apb_pclk"; }; uart0: serial@fe000000 { compatible = "arm,pl011", "arm,primecell";