From patchwork Wed Oct 14 13:19:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11837653 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA41761C for ; Wed, 14 Oct 2020 13:19:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A1AEA2222A for ; Wed, 14 Oct 2020 13:19:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="m9R1pokP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731186AbgJNNTt (ORCPT ); Wed, 14 Oct 2020 09:19:49 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:60134 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726810AbgJNNTr (ORCPT ); Wed, 14 Oct 2020 09:19:47 -0400 X-UUID: acdd2535599348b394a899c357c3b3c5-20201014 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0rbUbY5d6b/CqzMZNuO81lplf7j7vZlyTocLXWOmLaM=; b=m9R1pokPGauzmf59bT/trKuj/TH8qtbQQDy2yNSuUH4FAeFyT2rLbS4vYSjowpOJwnrbbbvWVfPlZmxtcuRtfVM+mfKnZ6MYzlHYOaophJ5CroFErjdlIjbq/nAMCSClbAK2QadlbshVmUusDoHVtiSZhqHisvUberq57EEttlo=; X-UUID: acdd2535599348b394a899c357c3b3c5-20201014 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2136793753; Wed, 14 Oct 2020 21:19:43 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Oct 2020 21:19:40 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 21:19:39 +0800 From: Crystal Guo To: , , , CC: , , , , , , Crystal Guo Subject: [v6,3/4] dt-binding: mt8192: add toprgu reset-controller head file Date: Wed, 14 Oct 2020 21:19:35 +0800 Message-ID: <20201014131936.20584-4-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201014131936.20584-1-crystal.guo@mediatek.com> References: <20201014131936.20584-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: F5A6F80AD7BD25478AC14C6C4E8CC7DB10719FD8D2B222C1A33C1090362E511C2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org add toprgu reset-controller head file for MT8192 platform Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Acked-by: Guenter Roeck --- .../reset-controller/mt8192-resets.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h new file mode 100644 index 000000000000..be9a7ca245b9 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8192-resets.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +#define MT8192_TOPRGU_MM_SW_RST 1 +#define MT8192_TOPRGU_MFG_SW_RST 2 +#define MT8192_TOPRGU_VENC_SW_RST 3 +#define MT8192_TOPRGU_VDEC_SW_RST 4 +#define MT8192_TOPRGU_IMG_SW_RST 5 +#define MT8192_TOPRGU_MD_SW_RST 7 +#define MT8192_TOPRGU_CONN_SW_RST 9 +#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8192_TOPRGU_IPU0_SW_RST 14 +#define MT8192_TOPRGU_IPU1_SW_RST 15 +#define MT8192_TOPRGU_AUDIO_SW_RST 17 +#define MT8192_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */