From patchwork Wed Oct 14 13:19:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11837655 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1608F1592 for ; Wed, 14 Oct 2020 13:19:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E24AF22242 for ; Wed, 14 Oct 2020 13:19:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="jo6wu60z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388309AbgJNNT5 (ORCPT ); Wed, 14 Oct 2020 09:19:57 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:53234 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728834AbgJNNTt (ORCPT ); Wed, 14 Oct 2020 09:19:49 -0400 X-UUID: 65b510f0281249dea5d9b02b76ed5fda-20201014 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MSvWctba+IbOd/a2WBji6T1/shGFuBINQUNZk7gS9c8=; b=jo6wu60zSS20sPXNU9xApHugOhYvGSyF6VKmMW7dOb/AzhLWn4XjsuWmuAk7y1tqLdp/JX1WZZlz+A3uQk1SXYSKIas+duw21YnZC6PKtAmLKI8H7Xpr57yv8bMph5CazFNxnTKstYM09AmLgDGYQfldfZhXU42QIybA5/g2wbI=; X-UUID: 65b510f0281249dea5d9b02b76ed5fda-20201014 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 457268610; Wed, 14 Oct 2020 21:19:43 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Oct 2020 21:19:40 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 21:19:40 +0800 From: Crystal Guo To: , , , CC: , , , , , , Crystal Guo Subject: [v6,4/4] watchdog: mt8192: add wdt support Date: Wed, 14 Oct 2020 21:19:36 +0800 Message-ID: <20201014131936.20584-5-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201014131936.20584-1-crystal.guo@mediatek.com> References: <20201014131936.20584-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add support for watchdog device found in MT8192 SoC Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Reviewed-by: Guenter Roeck --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393f609d..aef0c2db6a11 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt8192_data = { + .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, +}; + static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -322,6 +327,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);