@@ -23,7 +23,8 @@
#define TIM_WDOG_EN 0x8
#define TIM_SAFE 0xc
-#define WDT_ISR_MASK GENMASK(9, 8)
+#define WDT_TH_INT_MASK BIT(8)
+#define WDT_TO_INT_MASK BIT(9)
#define WDT_ISR_CLEAR 0x8200ff18
#define WDT_UNLOCK 0xf1d0dead
#define WDT_LOAD_MAX U32_MAX
@@ -142,7 +143,7 @@ static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id)
struct arm_smccc_res res;
keembay_wdt_writel(wdt, TIM_WATCHDOG, 1);
- arm_smccc_smc(WDT_ISR_CLEAR, WDT_ISR_MASK, 0, 0, 0, 0, 0, 0, &res);
+ arm_smccc_smc(WDT_ISR_CLEAR, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res);
dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt timeout.\n");
emergency_restart();
@@ -156,7 +157,7 @@ static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id)
keembay_wdt_set_pretimeout(&wdt->wdd, 0x0);
- arm_smccc_smc(WDT_ISR_CLEAR, WDT_ISR_MASK, 0, 0, 0, 0, 0, 0, &res);
+ arm_smccc_smc(WDT_ISR_CLEAR, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res);
dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt pre-timeout.\n");
watchdog_notify_pretimeout(&wdt->wdd);