From patchwork Thu Nov 4 16:08:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12603431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6452CC433EF for ; Thu, 4 Nov 2021 16:09:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4FB2260D43 for ; Thu, 4 Nov 2021 16:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231670AbhKDQLu (ORCPT ); Thu, 4 Nov 2021 12:11:50 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:34037 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231651AbhKDQLu (ORCPT ); Thu, 4 Nov 2021 12:11:50 -0400 X-IronPort-AV: E=Sophos;i="5.87,209,1631545200"; d="scan'208";a="99217962" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 05 Nov 2021 01:09:11 +0900 Received: from localhost.localdomain (unknown [10.226.92.57]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9A3964017749; Fri, 5 Nov 2021 01:09:09 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [RFC 3/4] clk: renesas: r9a07g044: Add WDT clock and reset entries Date: Thu, 4 Nov 2021 16:08:57 +0000 Message-Id: <20211104160858.15550-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104160858.15550-1-biju.das.jz@bp.renesas.com> References: <20211104160858.15550-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add WDT{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 8618b0f19d7a..79bad86b6cb7 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -146,6 +146,18 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, 0x52c, 1), + DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, + 0x548, 0), + DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, + 0x548, 1), + DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, + 0x548, 2), + DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, + 0x548, 3), + DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0, + 0x548, 4), + DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK, + 0x548, 5), DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, 0x550, 0), DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, @@ -234,6 +246,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), + DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), + DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2), DEF_RST(R9A07G044_SPI_RST, 0x850, 0), DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),