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[RFC,1/1] watchdog: imx2_wdg: suspend watchdog in WAIT mode

Message ID 20220921124647.1521667-2-andrej.picej@norik.com (mailing list archive)
State Superseded
Headers show
Series Suspending i.MX watchdog in WAIT mode | expand

Commit Message

Andrej Picej Sept. 21, 2022, 12:46 p.m. UTC 
Putting device into the "Suspend-To-Idle" mode causes watchdog to
trigger and reset the board after set watchdog timeout period elapses.
Setting WDW bit in WCR (Watchdog Control Register) suspends watchdog in
WAIT mode (corresponds to "Suspend-To-Idle" mode) and allows board to be
in idle for infinite amount of time. Watchdog operation is restored
after exiting WAIT mode as expected.

Signed-off-by: Andrej Picej <andrej.picej@norik.com>
---
 drivers/watchdog/imx2_wdt.c | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index 51bfb796898b..f888f29f50dd 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -35,6 +35,7 @@ 
 
 #define IMX2_WDT_WCR		0x00		/* Control Register */
 #define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
+#define IMX2_WDT_WCR_WDW	BIT(7)		/* -> Watchdog disable for WAIT */
 #define IMX2_WDT_WCR_WDA	BIT(5)		/* -> External Reset WDOG_B */
 #define IMX2_WDT_WCR_SRS	BIT(4)		/* -> Software Reset Signal */
 #define IMX2_WDT_WCR_WRE	BIT(3)		/* -> WDOG Reset Enable */
@@ -128,6 +129,8 @@  static inline void imx2_wdt_setup(struct watchdog_device *wdog)
 
 	/* Suspend timer in low power mode, write once-only */
 	val |= IMX2_WDT_WCR_WDZST;
+	/* Suspend timer in low power WAIT mode, write once-only */
+	val |= IMX2_WDT_WCR_WDW;
 	/* Strip the old watchdog Time-Out value */
 	val &= ~IMX2_WDT_WCR_WT;
 	/* Generate internal chip-level reset if WDOG times out */