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[88.10.60.23]) by smtp.gmail.com with ESMTPSA id c129-20020a1c3587000000b003dc1a525f22sm15591242wma.25.2023.02.13.12.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Feb 2023 12:05:24 -0800 (PST) From: Sergio Paracuellos To: linux-watchdog@vger.kernel.org Cc: wim@linux-watchdog.org, linux@roeck-us.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, arinc.unal@arinc9.com, tsbogend@alpha.franken.de, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v6 3/3] watchdog: mt7621-wdt: avoid ralink architecture dependent code Date: Mon, 13 Feb 2023 21:05:19 +0100 Message-Id: <20230213200519.889503-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230213200519.889503-1-sergio.paracuellos@gmail.com> References: <20230213200519.889503-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org MT7621 SoC has a system controller node. Watchdog need to access to reset status register. Ralink architecture and related driver are old and from the beggining they are using some architecture dependent operations for accessing this shared registers through 'asm/mach-ralink/ralink_regs.h' header file. However this is not ideal from a driver perspective which can just access to the system controller registers in an arch independent way using regmap syscon APIs. Update Kconfig accordingly to select new added dependencies and allow driver to be compile tested. Signed-off-by: Sergio Paracuellos --- drivers/watchdog/Kconfig | 4 +++- drivers/watchdog/mt7621_wdt.c | 18 +++++++++++++----- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b64bc49c7..cf752ad64 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1865,7 +1865,9 @@ config GXP_WATCHDOG config MT7621_WDT tristate "Mediatek SoC watchdog" select WATCHDOG_CORE - depends on SOC_MT7620 || SOC_MT7621 + select REGMAP_MMIO + select MFD_SYSCON + depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST help Hardware driver for the Mediatek/Ralink MT7621/8 SoC Watchdog Timer. diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c index 40fb2c9ba..22e979bdd 100644 --- a/drivers/watchdog/mt7621_wdt.c +++ b/drivers/watchdog/mt7621_wdt.c @@ -15,8 +15,8 @@ #include #include #include - -#include +#include +#include #define SYSC_RSTSTAT 0x38 #define WDT_RST_CAUSE BIT(1) @@ -34,6 +34,7 @@ struct mt7621_wdt_data { void __iomem *base; struct reset_control *rst; + struct regmap *sysc; struct watchdog_device wdt; }; @@ -104,9 +105,12 @@ static int mt7621_wdt_stop(struct watchdog_device *w) return 0; } -static int mt7621_wdt_bootcause(void) +static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d) { - if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) + u32 val; + + regmap_read(d->sysc, SYSC_RSTSTAT, &val); + if (val & WDT_RST_CAUSE) return WDIOF_CARDRESET; return 0; @@ -143,6 +147,10 @@ static int mt7621_wdt_probe(struct platform_device *pdev) if (!drvdata) return -ENOMEM; + drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc"); + if (IS_ERR(drvdata->sysc)) + return PTR_ERR(drvdata->sysc); + drvdata->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(drvdata->base)) return PTR_ERR(drvdata->base); @@ -158,7 +166,7 @@ static int mt7621_wdt_probe(struct platform_device *pdev) mt7621_wdt->max_timeout = 0xfffful / 1000; mt7621_wdt->parent = dev; - mt7621_wdt->bootstatus = mt7621_wdt_bootcause(); + mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata); watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev); watchdog_set_nowayout(mt7621_wdt, nowayout);