| Message ID | 20231010081909.2899101-3-ping.bai@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] wdog: imx7ulp: Enable wdog int_en bit for watchdog any reset | expand |
On Tue, Oct 10, 2023 at 04:19:09PM +0800, Jacky Bai wrote: > Add 'fsl,ext-reset-output' property for wdog3 to let it to trigger > external reset through wdog_any pin. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > Reviewed-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx93.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi > index f20dd18e0b65..bb40a022601d 100644 > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > @@ -562,6 +562,7 @@ wdog3: watchdog@42490000 { > interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&clk IMX93_CLK_WDOG3_GATE>; > timeout-sec = <40>; > + fsl,ext-reset-output; Shouldn't this be a board level setting? Shawn > status = "disabled"; > }; > > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index f20dd18e0b65..bb40a022601d 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -562,6 +562,7 @@ wdog3: watchdog@42490000 { interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_WDOG3_GATE>; timeout-sec = <40>; + fsl,ext-reset-output; status = "disabled"; };