From patchwork Fri Feb 25 12:01:01 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Natarajan X-Patchwork-Id: 589891 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p1PC1CsW023354 for ; Fri, 25 Feb 2011 12:01:13 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754832Ab1BYMBL (ORCPT ); Fri, 25 Feb 2011 07:01:11 -0500 Received: from mail.atheros.com ([12.19.149.2]:58237 "EHLO mail.atheros.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754452Ab1BYMBK (ORCPT ); Fri, 25 Feb 2011 07:01:10 -0500 Received: from mail.atheros.com ([10.10.20.105]) by sidewinder.atheros.com for ; Fri, 25 Feb 2011 04:00:49 -0800 Received: from smtp.atheros.com (10.12.4.8) by SC1EXHC-01.global.atheros.com (10.10.20.111) with Microsoft SMTP Server (TLS) id 8.2.213.0; Fri, 25 Feb 2011 04:01:08 -0800 Received: by smtp.atheros.com (sSMTP sendmail emulation); Fri, 25 Feb 2011 17:31:03 +0530 From: Vivek Natarajan To: CC: Subject: [PATCH 1/3] ath9k_hw: Fix pcie_serdes setting for AR9485 1.1 version. Date: Fri, 25 Feb 2011 17:31:01 +0530 Message-ID: <1298635263-4883-1-git-send-email-vnatarajan@atheros.com> X-Mailer: git-send-email 1.6.3.3 MIME-Version: 1.0 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 25 Feb 2011 12:01:13 +0000 (UTC) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index 6fa3c24..7f5de6e 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -78,15 +78,15 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) /* Awake Setting */ INIT_INI_ARRAY(&ah->iniPcieSerdes, - ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1, - ARRAY_SIZE(ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1), + ar9485_1_1_pcie_phy_clkreq_disable_L1, + ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), 2); /* Sleep Setting */ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, - ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1, - ARRAY_SIZE(ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1), + ar9485_1_1_pcie_phy_clkreq_disable_L1, + ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), 2); } else if (AR_SREV_9485(ah)) { /* mac */