From patchwork Wed May 4 08:53:52 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasanthakumar Thiagarajan X-Patchwork-Id: 753042 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p448l4eb019561 for ; Wed, 4 May 2011 08:47:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752094Ab1EDIrA (ORCPT ); Wed, 4 May 2011 04:47:00 -0400 Received: from mail.atheros.com ([12.19.149.2]:32950 "EHLO mail.atheros.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751903Ab1EDIq4 (ORCPT ); Wed, 4 May 2011 04:46:56 -0400 Received: from mail.atheros.com ([10.10.20.108]) by sidewinder.atheros.com for ; Wed, 04 May 2011 01:46:27 -0700 Received: from CHEXHC-01.global.atheros.com (10.12.0.100) by SC1EXHC-02.global.atheros.com (10.234.20.107) with Microsoft SMTP Server (TLS) id 8.2.213.0; Wed, 4 May 2011 01:46:55 -0700 Received: from smtpch.atheros.com (10.12.4.43) by CHEXHC-01.global.atheros.com (10.12.0.100) with Microsoft SMTP Server (TLS) id 8.2.176.0; Wed, 4 May 2011 14:16:28 +0530 Received: by smtpch.atheros.com (sSMTP sendmail emulation); Wed, 04 May 2011 14:23:58 +0530 From: Vasanthakumar Thiagarajan To: CC: , , , , "Vasanthakumar Thiagarajan" Subject: [PATCH 1/5] ath6kl: Remove somemore unused header files Date: Wed, 4 May 2011 14:23:52 +0530 Message-ID: <1304499236-10092-1-git-send-email-vasanth@atheros.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 04 May 2011 08:47:04 +0000 (UTC) Signed-off-by: Vasanthakumar Thiagarajan --- .../include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h | 195 ------ drivers/staging/ath6kl/include/common/a_hci.h | 682 -------------------- .../staging/ath6kl/include/common/dset_internal.h | 55 -- drivers/staging/ath6kl/include/common/dsetid.h | 126 ---- .../include/common/regulatory/reg_dbschema.h | 237 ------- .../include/common/regulatory/reg_dbvalues.h | 504 --------------- drivers/staging/ath6kl/include/common/wmi_thin.h | 347 ---------- drivers/staging/ath6kl/include/target_reg_table.h | 244 ------- 8 files changed, 0 insertions(+), 2390 deletions(-) delete mode 100644 drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h delete mode 100644 drivers/staging/ath6kl/include/common/a_hci.h delete mode 100644 drivers/staging/ath6kl/include/common/dset_internal.h delete mode 100644 drivers/staging/ath6kl/include/common/dsetid.h delete mode 100644 drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h delete mode 100644 drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h delete mode 100644 drivers/staging/ath6kl/include/common/wmi_thin.h delete mode 100644 drivers/staging/ath6kl/include/target_reg_table.h diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h deleted file mode 100644 index d28de39..0000000 --- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h +++ /dev/null @@ -1,195 +0,0 @@ -// ------------------------------------------------------------------ -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -// ------------------------------------------------------------------ -//=================================================================== -// Author(s): ="Atheros" -//=================================================================== - - -#ifndef _VMC_WLAN_REG_REG_H_ -#define _VMC_WLAN_REG_REG_H_ - -#define WLAN_MC_BCAM_VALID_ADDRESS 0x00000000 -#define WLAN_MC_BCAM_VALID_OFFSET 0x00000000 -#define WLAN_MC_BCAM_VALID_BIT_MSB 0 -#define WLAN_MC_BCAM_VALID_BIT_LSB 0 -#define WLAN_MC_BCAM_VALID_BIT_MASK 0x00000001 -#define WLAN_MC_BCAM_VALID_BIT_GET(x) (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB) -#define WLAN_MC_BCAM_VALID_BIT_SET(x) (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK) - -#define WLAN_MC_BCAM_COMPARE_ADDRESS 0x00000200 -#define WLAN_MC_BCAM_COMPARE_OFFSET 0x00000200 -#define WLAN_MC_BCAM_COMPARE_KEY_MSB 19 -#define WLAN_MC_BCAM_COMPARE_KEY_LSB 2 -#define WLAN_MC_BCAM_COMPARE_KEY_MASK 0x000ffffc -#define WLAN_MC_BCAM_COMPARE_KEY_GET(x) (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB) -#define WLAN_MC_BCAM_COMPARE_KEY_SET(x) (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK) - -#define WLAN_MC_BCAM_TARGET_ADDRESS 0x00000400 -#define WLAN_MC_BCAM_TARGET_OFFSET 0x00000400 -#define WLAN_MC_BCAM_TARGET_INST_MSB 31 -#define WLAN_MC_BCAM_TARGET_INST_LSB 0 -#define WLAN_MC_BCAM_TARGET_INST_MASK 0xffffffff -#define WLAN_MC_BCAM_TARGET_INST_GET(x) (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB) -#define WLAN_MC_BCAM_TARGET_INST_SET(x) (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK) - -#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS 0x00000600 -#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET 0x00000600 -#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 -#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 -#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 -#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) -#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) -#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB 0 -#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB 0 -#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 -#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) -#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) - -#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS 0x00000604 -#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET 0x00000604 -#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB 25 -#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB 25 -#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 -#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) -#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) -#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB 24 -#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB 0 -#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff -#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) -#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) - -#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS 0x00000608 -#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET 0x00000608 -#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB 0 -#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB 0 -#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 -#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) -#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) - -#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS 0x0000060c -#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET 0x0000060c -#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB 31 -#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB 31 -#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK 0x80000000 -#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) -#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) -#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB 30 -#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB 30 -#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK 0x40000000 -#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) -#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) -#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB 23 -#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB 0 -#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x00ffffff -#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) -#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) - -#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS 0x00000610 -#define WLAN_BCAM_CONFLICT_ERROR_OFFSET 0x00000610 -#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB 1 -#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB 1 -#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002 -#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) -#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) -#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB 0 -#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB 0 -#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001 -#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) -#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) - -#define WLAN_CPU_PERF_CNT_ADDRESS 0x00000614 -#define WLAN_CPU_PERF_CNT_OFFSET 0x00000614 -#define WLAN_CPU_PERF_CNT_EN_MSB 0 -#define WLAN_CPU_PERF_CNT_EN_LSB 0 -#define WLAN_CPU_PERF_CNT_EN_MASK 0x00000001 -#define WLAN_CPU_PERF_CNT_EN_GET(x) (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB) -#define WLAN_CPU_PERF_CNT_EN_SET(x) (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK) - -#define WLAN_CPU_INST_FETCH_ADDRESS 0x00000618 -#define WLAN_CPU_INST_FETCH_OFFSET 0x00000618 -#define WLAN_CPU_INST_FETCH_CNT_MSB 31 -#define WLAN_CPU_INST_FETCH_CNT_LSB 0 -#define WLAN_CPU_INST_FETCH_CNT_MASK 0xffffffff -#define WLAN_CPU_INST_FETCH_CNT_GET(x) (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB) -#define WLAN_CPU_INST_FETCH_CNT_SET(x) (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK) - -#define WLAN_CPU_DATA_FETCH_ADDRESS 0x0000061c -#define WLAN_CPU_DATA_FETCH_OFFSET 0x0000061c -#define WLAN_CPU_DATA_FETCH_CNT_MSB 31 -#define WLAN_CPU_DATA_FETCH_CNT_LSB 0 -#define WLAN_CPU_DATA_FETCH_CNT_MASK 0xffffffff -#define WLAN_CPU_DATA_FETCH_CNT_GET(x) (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB) -#define WLAN_CPU_DATA_FETCH_CNT_SET(x) (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK) - -#define WLAN_CPU_RAM1_CONFLICT_ADDRESS 0x00000620 -#define WLAN_CPU_RAM1_CONFLICT_OFFSET 0x00000620 -#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB 11 -#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB 0 -#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK 0x00000fff -#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB) -#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) - -#define WLAN_CPU_RAM2_CONFLICT_ADDRESS 0x00000624 -#define WLAN_CPU_RAM2_CONFLICT_OFFSET 0x00000624 -#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB 11 -#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB 0 -#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK 0x00000fff -#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB) -#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) - -#define WLAN_CPU_RAM3_CONFLICT_ADDRESS 0x00000628 -#define WLAN_CPU_RAM3_CONFLICT_OFFSET 0x00000628 -#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB 11 -#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB 0 -#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK 0x00000fff -#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB) -#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) - -#define WLAN_CPU_RAM4_CONFLICT_ADDRESS 0x0000062c -#define WLAN_CPU_RAM4_CONFLICT_OFFSET 0x0000062c -#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB 11 -#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB 0 -#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK 0x00000fff -#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB) -#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) - - -#ifndef __ASSEMBLER__ - -typedef struct vmc_wlan_reg_reg_s { - volatile unsigned int wlan_mc_bcam_valid[128]; - volatile unsigned int wlan_mc_bcam_compare[128]; - volatile unsigned int wlan_mc_bcam_target[128]; - volatile unsigned int wlan_apb_addr_error_control; - volatile unsigned int wlan_apb_addr_error_status; - volatile unsigned int wlan_ahb_addr_error_control; - volatile unsigned int wlan_ahb_addr_error_status; - volatile unsigned int wlan_bcam_conflict_error; - volatile unsigned int wlan_cpu_perf_cnt; - volatile unsigned int wlan_cpu_inst_fetch; - volatile unsigned int wlan_cpu_data_fetch; - volatile unsigned int wlan_cpu_ram1_conflict; - volatile unsigned int wlan_cpu_ram2_conflict; - volatile unsigned int wlan_cpu_ram3_conflict; - volatile unsigned int wlan_cpu_ram4_conflict; -} vmc_wlan_reg_reg_t; - -#endif /* __ASSEMBLER__ */ - -#endif /* _VMC_WLAN_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/a_hci.h b/drivers/staging/ath6kl/include/common/a_hci.h deleted file mode 100644 index 379d652..0000000 --- a/drivers/staging/ath6kl/include/common/a_hci.h +++ /dev/null @@ -1,682 +0,0 @@ -//- -// Copyright (c) 2009-2010 Atheros Communications Inc. -// All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -// -// - - -#ifndef __A_HCI_H__ -#define __A_HCI_H__ - -#define HCI_CMD_OGF_MASK 0x3F -#define HCI_CMD_OGF_SHIFT 10 -#define HCI_CMD_GET_OGF(opcode) ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK) - -#define HCI_CMD_OCF_MASK 0x3FF -#define HCI_CMD_OCF_SHIFT 0 -#define HCI_CMD_GET_OCF(opcode) (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK) - -#define HCI_FORM_OPCODE(ocf, ogf) ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \ - (ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT) - - -/*======== HCI Opcode groups ===============*/ -#define OGF_NOP 0x00 -#define OGF_LINK_CONTROL 0x01 -#define OGF_LINK_POLICY 0x03 -#define OGF_INFO_PARAMS 0x04 -#define OGF_STATUS 0x05 -#define OGF_TESTING 0x06 -#define OGF_BLUETOOTH 0x3E -#define OGF_VENDOR_DEBUG 0x3F - - - -#define OCF_NOP 0x00 - - -/*===== Link Control Commands Opcode===================*/ -#define OCF_HCI_Create_Physical_Link 0x35 -#define OCF_HCI_Accept_Physical_Link_Req 0x36 -#define OCF_HCI_Disconnect_Physical_Link 0x37 -#define OCF_HCI_Create_Logical_Link 0x38 -#define OCF_HCI_Accept_Logical_Link 0x39 -#define OCF_HCI_Disconnect_Logical_Link 0x3A -#define OCF_HCI_Logical_Link_Cancel 0x3B -#define OCF_HCI_Flow_Spec_Modify 0x3C - - - -/*===== Link Policy Commands Opcode====================*/ -#define OCF_HCI_Set_Event_Mask 0x01 -#define OCF_HCI_Reset 0x03 -#define OCF_HCI_Read_Conn_Accept_Timeout 0x15 -#define OCF_HCI_Write_Conn_Accept_Timeout 0x16 -#define OCF_HCI_Read_Link_Supervision_Timeout 0x36 -#define OCF_HCI_Write_Link_Supervision_Timeout 0x37 -#define OCF_HCI_Enhanced_Flush 0x5F -#define OCF_HCI_Read_Logical_Link_Accept_Timeout 0x61 -#define OCF_HCI_Write_Logical_Link_Accept_Timeout 0x62 -#define OCF_HCI_Set_Event_Mask_Page_2 0x63 -#define OCF_HCI_Read_Location_Data 0x64 -#define OCF_HCI_Write_Location_Data 0x65 -#define OCF_HCI_Read_Flow_Control_Mode 0x66 -#define OCF_HCI_Write_Flow_Control_Mode 0x67 -#define OCF_HCI_Read_BE_Flush_Timeout 0x69 -#define OCF_HCI_Write_BE_Flush_Timeout 0x6A -#define OCF_HCI_Short_Range_Mode 0x6B - - -/*======== Info Commands Opcode========================*/ -#define OCF_HCI_Read_Local_Ver_Info 0x01 -#define OCF_HCI_Read_Local_Supported_Cmds 0x02 -#define OCF_HCI_Read_Data_Block_Size 0x0A -/*======== Status Commands Opcode======================*/ -#define OCF_HCI_Read_Failed_Contact_Counter 0x01 -#define OCF_HCI_Reset_Failed_Contact_Counter 0x02 -#define OCF_HCI_Read_Link_Quality 0x03 -#define OCF_HCI_Read_RSSI 0x05 -#define OCF_HCI_Read_Local_AMP_Info 0x09 -#define OCF_HCI_Read_Local_AMP_ASSOC 0x0A -#define OCF_HCI_Write_Remote_AMP_ASSOC 0x0B - - -/*======= AMP_ASSOC Specific TLV tags =================*/ -#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE 0x1 -#define AMP_ASSOC_PREF_CHAN_LIST 0x2 -#define AMP_ASSOC_CONNECTED_CHAN 0x3 -#define AMP_ASSOC_PAL_CAPABILITIES 0x4 -#define AMP_ASSOC_PAL_VERSION 0x5 - - -/*========= PAL Events =================================*/ -#define PAL_COMMAND_COMPLETE_EVENT 0x0E -#define PAL_COMMAND_STATUS_EVENT 0x0F -#define PAL_HARDWARE_ERROR_EVENT 0x10 -#define PAL_FLUSH_OCCURRED_EVENT 0x11 -#define PAL_LOOPBACK_EVENT 0x19 -#define PAL_BUFFER_OVERFLOW_EVENT 0x1A -#define PAL_QOS_VIOLATION_EVENT 0x1E -#define PAL_ENHANCED_FLUSH_COMPLT_EVENT 0x39 -#define PAL_PHYSICAL_LINK_COMPL_EVENT 0x40 -#define PAL_CHANNEL_SELECT_EVENT 0x41 -#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT 0x42 -#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT 0x43 -#define PAL_PHY_LINK_RECOVERY_EVENT 0x44 -#define PAL_LOGICAL_LINK_COMPL_EVENT 0x45 -#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT 0x46 -#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT 0x47 -#define PAL_NUM_COMPL_DATA_BLOCK_EVENT 0x48 -#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT 0x4C -#define PAL_AMP_STATUS_CHANGE_EVENT 0x4D -/*======== End of PAL events definition =================*/ - - -/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/ -#define Timer_Conn_Accept_TO 0x01 -#define Timer_Link_Supervision_TO 0x02 - -#define NUM_HCI_COMMAND_PKTS 0x1 - - -/*====== NOP Cmd ============================*/ -#define HCI_CMD_NOP HCI_FORM_OPCODE(OCF_NOP, OGF_NOP) - - -/*===== Link Control Commands================*/ -#define HCI_Create_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL) -#define HCI_Accept_Physical_Link_Req HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL) -#define HCI_Disconnect_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL) -#define HCI_Create_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL) -#define HCI_Accept_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL) -#define HCI_Disconnect_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL) -#define HCI_Logical_Link_Cancel HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL) -#define HCI_Flow_Spec_Modify HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL) - - -/*===== Link Policy Commands ================*/ -#define HCI_Set_Event_Mask HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY) -#define HCI_Reset HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY) -#define HCI_Enhanced_Flush HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY) -#define HCI_Read_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY) -#define HCI_Write_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY) -#define HCI_Read_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY) -#define HCI_Write_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY) -#define HCI_Read_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY) -#define HCI_Write_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY) -#define HCI_Read_Location_Data HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY) -#define HCI_Write_Location_Data HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY) -#define HCI_Set_Event_Mask_Page_2 HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY) -#define HCI_Read_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY) -#define HCI_Write_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY) -#define HCI_Write_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY) -#define HCI_Read_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY) -#define HCI_Short_Range_Mode HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY) - - -/*===== Info Commands =====================*/ -#define HCI_Read_Local_Ver_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info, OGF_INFO_PARAMS) -#define HCI_Read_Local_Supported_Cmds HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS) -#define HCI_Read_Data_Block_Size HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS) - -/*===== Status Commands =====================*/ -#define HCI_Read_Link_Quality HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS) -#define HCI_Read_RSSI HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS) -#define HCI_Read_Local_AMP_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS) -#define HCI_Read_Local_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS) -#define HCI_Write_Remote_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS) - -/*====== End of cmd definitions =============*/ - - - -/*===== Timeouts(private - can't come from HCI)=================*/ -#define Conn_Accept_TO HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG) -#define Link_Supervision_TO HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG) - -/*----- PAL Constants (Sec 6 of Doc)------------------------*/ -#define Max80211_PAL_PDU_Size 1492 -#define Max80211_AMP_ASSOC_Len 672 -#define MinGUserPrio 4 -#define MaxGUserPrio 7 -#define BEUserPrio0 0 -#define BEUserPrio1 3 -#define Max80211BeaconPeriod 2000 /* in millisec */ -#define ShortRangeModePowerMax 4 /* dBm */ - -/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/ -typedef enum { - ACL_DATA = 0x01, - ACTIVITY_REPORT, - SECURED_FRAMES, - LINK_SUPERVISION_REQ, - LINK_SUPERVISION_RESP, -}PAL_PROTOCOL_IDENTIFIERS; - -#define HCI_CMD_HDR_SZ 3 -#define HCI_EVENT_HDR_SIZE 2 -#define MAX_EVT_PKT_SZ 255 -#define AMP_ASSOC_MAX_FRAG_SZ 248 -#define AMP_MAX_GUARANTEED_BW 20000 - -#define DEFAULT_CONN_ACCPT_TO 5000 -#define DEFAULT_LL_ACCPT_TO 5000 -#define DEFAULT_LSTO 10000 - -#define PACKET_BASED_FLOW_CONTROL_MODE 0x00 -#define DATA_BLK_BASED_FLOW_CONTROL_MODE 0x01 - -#define SERVICE_TYPE_BEST_EFFORT 0x01 -#define SERVICE_TYPE_GUARANTEED 0x02 - -#define MAC_ADDR_LEN 6 -#define LINK_KEY_LEN 32 - -typedef enum { - ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00, - ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01, - ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02, - ACL_DATA_PB_COMPLETE_PDU = 0x03, -} ACL_DATA_PB_FLAGS; -#define ACL_DATA_PB_FLAGS_SHIFT 12 - -typedef enum { - ACL_DATA_BC_POINT_TO_POINT = 0x00, -} ACL_DATA_BC_FLAGS; -#define ACL_DATA_BC_FLAGS_SHIFT 14 - -/* Command pkt */ -typedef struct hci_cmd_pkt_t { - u16 opcode; - u8 param_length; - u8 params[255]; -} POSTPACK HCI_CMD_PKT; - -#define ACL_DATA_HDR_SIZE 4 /* hdl_and flags + data_len */ -/* Data pkt */ -typedef struct hci_acl_data_pkt_t { - u16 hdl_and_flags; - u16 data_len; - u8 data[Max80211_PAL_PDU_Size]; -} POSTPACK HCI_ACL_DATA_PKT; - -/* Event pkt */ -typedef struct hci_event_pkt_t { - u8 event_code; - u8 param_len; - u8 params[256]; -} POSTPACK HCI_EVENT_PKT; - - -/*============== HCI Command definitions ======================= */ -typedef struct hci_cmd_phy_link_t { - u16 opcode; - u8 param_length; - u8 phy_link_hdl; - u8 link_key_len; - u8 link_key_type; - u8 link_key[LINK_KEY_LEN]; -} POSTPACK HCI_CMD_PHY_LINK; - -typedef struct hci_cmd_write_rem_amp_assoc_t { - u16 opcode; - u8 param_length; - u8 phy_link_hdl; - u16 len_so_far; - u16 amp_assoc_remaining_len; - u8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ]; -} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC; - - -typedef struct hci_cmd_opcode_hdl_t { - u16 opcode; - u8 param_length; - u16 hdl; -} POSTPACK HCI_CMD_READ_LINK_QUAL, - HCI_CMD_FLUSH, - HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT; - -typedef struct hci_cmd_read_local_amp_assoc_t { - u16 opcode; - u8 param_length; - u8 phy_link_hdl; - u16 len_so_far; - u16 max_rem_amp_assoc_len; -} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC; - - -typedef struct hci_cmd_set_event_mask_t { - u16 opcode; - u8 param_length; - u64 mask; -}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2; - - -typedef struct hci_cmd_enhanced_flush_t{ - u16 opcode; - u8 param_length; - u16 hdl; - u8 type; -} POSTPACK HCI_CMD_ENHANCED_FLUSH; - - -typedef struct hci_cmd_write_timeout_t { - u16 opcode; - u8 param_length; - u16 timeout; -} POSTPACK HCI_CMD_WRITE_TIMEOUT; - -typedef struct hci_cmd_write_link_supervision_timeout_t { - u16 opcode; - u8 param_length; - u16 hdl; - u16 timeout; -} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT; - -typedef struct hci_cmd_write_flow_control_t { - u16 opcode; - u8 param_length; - u8 mode; -} POSTPACK HCI_CMD_WRITE_FLOW_CONTROL; - -typedef struct location_data_cfg_t { - u8 reg_domain_aware; - u8 reg_domain[3]; - u8 reg_options; -} POSTPACK LOCATION_DATA_CFG; - -typedef struct hci_cmd_write_location_data_t { - u16 opcode; - u8 param_length; - LOCATION_DATA_CFG cfg; -} POSTPACK HCI_CMD_WRITE_LOCATION_DATA; - - -typedef struct flow_spec_t { - u8 id; - u8 service_type; - u16 max_sdu; - u32 sdu_inter_arrival_time; - u32 access_latency; - u32 flush_timeout; -} POSTPACK FLOW_SPEC; - - -typedef struct hci_cmd_create_logical_link_t { - u16 opcode; - u8 param_length; - u8 phy_link_hdl; - FLOW_SPEC tx_flow_spec; - FLOW_SPEC rx_flow_spec; -} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK; - -typedef struct hci_cmd_flow_spec_modify_t { - u16 opcode; - u8 param_length; - u16 hdl; - FLOW_SPEC tx_flow_spec; - FLOW_SPEC rx_flow_spec; -} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY; - -typedef struct hci_cmd_logical_link_cancel_t { - u16 opcode; - u8 param_length; - u8 phy_link_hdl; - u8 tx_flow_spec_id; -} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL; - -typedef struct hci_cmd_disconnect_logical_link_t { - u16 opcode; - u8 param_length; - u16 logical_link_hdl; -} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK; - -typedef struct hci_cmd_disconnect_phy_link_t { - u16 opcode; - u8 param_length; - u8 phy_link_hdl; -} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK; - -typedef struct hci_cmd_srm_t { - u16 opcode; - u8 param_length; - u8 phy_link_hdl; - u8 mode; -} POSTPACK HCI_CMD_SHORT_RANGE_MODE; -/*============== HCI Command definitions end ======================= */ - - - -/*============== HCI Event definitions ============================= */ - -/* Command complete event */ -typedef struct hci_event_cmd_complete_t { - u8 event_code; - u8 param_len; - u8 num_hci_cmd_pkts; - u16 opcode; - u8 params[255]; -} POSTPACK HCI_EVENT_CMD_COMPLETE; - - -/* Command status event */ -typedef struct hci_event_cmd_status_t { - u8 event_code; - u8 param_len; - u8 status; - u8 num_hci_cmd_pkts; - u16 opcode; -} POSTPACK HCI_EVENT_CMD_STATUS; - -/* Hardware Error event */ -typedef struct hci_event_hw_err_t { - u8 event_code; - u8 param_len; - u8 hw_err_code; -} POSTPACK HCI_EVENT_HW_ERR; - -/* Flush occurred event */ -/* Qos Violation event */ -typedef struct hci_event_handle_t { - u8 event_code; - u8 param_len; - u16 handle; -} POSTPACK HCI_EVENT_FLUSH_OCCRD, - HCI_EVENT_QOS_VIOLATION; - -/* Loopback command event */ -typedef struct hci_loopback_cmd_t { - u8 event_code; - u8 param_len; - u8 params[252]; -} POSTPACK HCI_EVENT_LOOPBACK_CMD; - -/* Data buffer overflow event */ -typedef struct hci_data_buf_overflow_t { - u8 event_code; - u8 param_len; - u8 link_type; -} POSTPACK HCI_EVENT_DATA_BUF_OVERFLOW; - -/* Enhanced Flush complete event */ -typedef struct hci_enhanced_flush_complt_t{ - u8 event_code; - u8 param_len; - u16 hdl; -} POSTPACK HCI_EVENT_ENHANCED_FLUSH_COMPLT; - -/* Channel select event */ -typedef struct hci_event_chan_select_t { - u8 event_code; - u8 param_len; - u8 phy_link_hdl; -} POSTPACK HCI_EVENT_CHAN_SELECT; - -/* Physical Link Complete event */ -typedef struct hci_event_phy_link_complete_event_t { - u8 event_code; - u8 param_len; - u8 status; - u8 phy_link_hdl; -} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE; - -/* Logical Link complete event */ -typedef struct hci_event_logical_link_complete_event_t { - u8 event_code; - u8 param_len; - u8 status; - u16 logical_link_hdl; - u8 phy_hdl; - u8 tx_flow_id; -} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT; - -/* Disconnect Logical Link complete event */ -typedef struct hci_event_disconnect_logical_link_event_t { - u8 event_code; - u8 param_len; - u8 status; - u16 logical_link_hdl; - u8 reason; -} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT; - -/* Disconnect Physical Link complete event */ -typedef struct hci_event_disconnect_phy_link_complete_t { - u8 event_code; - u8 param_len; - u8 status; - u8 phy_link_hdl; - u8 reason; -} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE; - -typedef struct hci_event_physical_link_loss_early_warning_t{ - u8 event_code; - u8 param_len; - u8 phy_hdl; - u8 reason; -} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING; - -typedef struct hci_event_physical_link_recovery_t{ - u8 event_code; - u8 param_len; - u8 phy_hdl; -} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY; - - -/* Flow spec modify complete event */ -/* Flush event */ -typedef struct hci_event_status_handle_t { - u8 event_code; - u8 param_len; - u8 status; - u16 handle; -} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY, - HCI_EVENT_FLUSH; - - -/* Num of completed data blocks event */ -typedef struct hci_event_num_of_compl_data_blks_t { - u8 event_code; - u8 param_len; - u16 num_data_blks; - u8 num_handles; - u8 params[255]; -} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS; - -/* Short range mode change complete event */ -typedef struct hci_srm_cmpl_t { - u8 event_code; - u8 param_len; - u8 status; - u8 phy_link; - u8 state; -} POSTPACK HCI_EVENT_SRM_COMPL; - -typedef struct hci_event_amp_status_change_t{ - u8 event_code; - u8 param_len; - u8 status; - u8 amp_status; -} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE; - -/*============== Event definitions end =========================== */ - - -typedef struct local_amp_info_resp_t { - u8 status; - u8 amp_status; - u32 total_bw; /* kbps */ - u32 max_guranteed_bw; /* kbps */ - u32 min_latency; - u32 max_pdu_size; - u8 amp_type; - u16 pal_capabilities; - u16 amp_assoc_len; - u32 max_flush_timeout; /* in ms */ - u32 be_flush_timeout; /* in ms */ -} POSTPACK LOCAL_AMP_INFO; - -typedef struct amp_assoc_cmd_resp_t{ - u8 status; - u8 phy_hdl; - u16 amp_assoc_len; - u8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ]; -}POSTPACK AMP_ASSOC_CMD_RESP; - - -enum PAL_HCI_CMD_STATUS { - PAL_HCI_CMD_PROCESSED, - PAL_HCI_CMD_IGNORED -}; - - -/*============= HCI Error Codes =======================*/ -#define HCI_SUCCESS 0x00 -#define HCI_ERR_UNKNOW_CMD 0x01 -#define HCI_ERR_UNKNOWN_CONN_ID 0x02 -#define HCI_ERR_HW_FAILURE 0x03 -#define HCI_ERR_PAGE_TIMEOUT 0x04 -#define HCI_ERR_AUTH_FAILURE 0x05 -#define HCI_ERR_KEY_MISSING 0x06 -#define HCI_ERR_MEM_CAP_EXECED 0x07 -#define HCI_ERR_CON_TIMEOUT 0x08 -#define HCI_ERR_CON_LIMIT_EXECED 0x09 -#define HCI_ERR_ACL_CONN_ALRDY_EXISTS 0x0B -#define HCI_ERR_COMMAND_DISALLOWED 0x0C -#define HCI_ERR_CONN_REJ_BY_LIMIT_RES 0x0D -#define HCI_ERR_CONN_REJ_BY_SEC 0x0E -#define HCI_ERR_CONN_REJ_BY_BAD_ADDR 0x0F -#define HCI_ERR_CONN_ACCPT_TIMEOUT 0x10 -#define HCI_ERR_UNSUPPORT_FEATURE 0x11 -#define HCI_ERR_INVALID_HCI_CMD_PARAMS 0x12 -#define HCI_ERR_REMOTE_USER_TERMINATE_CONN 0x13 -#define HCI_ERR_CON_TERM_BY_HOST 0x16 -#define HCI_ERR_UNSPECIFIED_ERROR 0x1F -#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT 0x25 -#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT 0x27 -#define HCI_ERR_QOS_UNACCEPTABLE_PARM 0x2C -#define HCI_ERR_QOS_REJECTED 0x2D -#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN 0x39 - -/*============= HCI Error Codes End =======================*/ - - -/* Following are event return parameters.. part of HCI events - */ -typedef struct timeout_read_t { - u8 status; - u16 timeout; -}POSTPACK TIMEOUT_INFO; - -typedef struct link_supervision_timeout_read_t { - u8 status; - u16 hdl; - u16 timeout; -}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO; - -typedef struct status_hdl_t { - u8 status; - u16 hdl; -}POSTPACK INFO_STATUS_HDL; - -typedef struct write_remote_amp_assoc_t{ - u8 status; - u8 hdl; -}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO; - -typedef struct read_loc_info_t { - u8 status; - LOCATION_DATA_CFG loc; -}POSTPACK READ_LOC_INFO; - -typedef struct read_flow_ctrl_mode_t { - u8 status; - u8 mode; -}POSTPACK READ_FLWCTRL_INFO; - -typedef struct read_data_blk_size_t { - u8 status; - u16 max_acl_data_pkt_len; - u16 data_block_len; - u16 total_num_data_blks; -}POSTPACK READ_DATA_BLK_SIZE_INFO; - -/* Read Link quality info */ -typedef struct link_qual_t { - u8 status; - u16 hdl; - u8 link_qual; -} POSTPACK READ_LINK_QUAL_INFO, - READ_RSSI_INFO; - -typedef struct ll_cancel_resp_t { - u8 status; - u8 phy_link_hdl; - u8 tx_flow_spec_id; -} POSTPACK LL_CANCEL_RESP; - -typedef struct read_local_ver_info_t { - u8 status; - u8 hci_version; - u16 hci_revision; - u8 pal_version; - u16 manf_name; - u16 pal_sub_ver; -} POSTPACK READ_LOCAL_VER_INFO; - - -#endif /* __A_HCI_H__ */ diff --git a/drivers/staging/ath6kl/include/common/dset_internal.h b/drivers/staging/ath6kl/include/common/dset_internal.h deleted file mode 100644 index e3ecd8e..0000000 --- a/drivers/staging/ath6kl/include/common/dset_internal.h +++ /dev/null @@ -1,55 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -//------------------------------------------------------------------------------ -//============================================================================== -// Author(s): ="Atheros" -//============================================================================== - - -#ifndef __DSET_INTERNAL_H__ -#define __DSET_INTERNAL_H__ - -/* - * Internal dset definitions, common for DataSet layer. - */ - -#define DSET_TYPE_STANDARD 0 -#define DSET_TYPE_BPATCHED 1 -#define DSET_TYPE_COMPRESSED 2 - -/* Dataset descriptor */ - -typedef PREPACK struct dset_descriptor_s { - struct dset_descriptor_s *next; /* List link. NULL only at the last - descriptor */ - u16 id; /* Dset ID */ - u16 size; /* Dset size. */ - void *DataPtr; /* Pointer to raw data for standard - DataSet or pointer to original - dset_descriptor for patched - DataSet */ - u32 data_type; /* DSET_TYPE_*, above */ - - void *AuxPtr; /* Additional data that might - needed for data_type. For - example, pointer to patch - Dataset descriptor for BPatch. */ -} POSTPACK dset_descriptor_t; - -#endif /* __DSET_INTERNAL_H__ */ diff --git a/drivers/staging/ath6kl/include/common/dsetid.h b/drivers/staging/ath6kl/include/common/dsetid.h deleted file mode 100644 index cc797ba..0000000 --- a/drivers/staging/ath6kl/include/common/dsetid.h +++ /dev/null @@ -1,126 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -//------------------------------------------------------------------------------ -//============================================================================== -// Author(s): ="Atheros" -//============================================================================== - - -#ifndef __DSETID_H__ -#define __DSETID_H__ - -/* Well-known DataSet IDs */ -#define DSETID_UNUSED 0x00000000 -#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */ -#define DSETID_REGDB 0x00000002 /* Regulatory Database */ -#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */ -#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */ - -#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005 -#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025 -/* - * Get DSETID for various reference clock speeds. - * For each speed there are three DataSets that correspond - * to the three columns of bank6 data (addr, 11a, 11b/g). - * This macro returns the dsetid of the first of those - * three DataSets. - */ -#define ANALOG_CONTROL_DATA_DSETID(refclk) \ - (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk) - -/* - * There are TWO STARTUP_PATCH DataSets. - * DSETID_STARTUP_PATCH is historical, and was applied before BMI on - * earlier systems. On AR6002, it is applied after BMI, just like - * DSETID_STARTUP_PATCH2. - */ -#define DSETID_STARTUP_PATCH 0x00000026 -#define DSETID_GPIO_CONFIG_PATCH 0x00000027 -#define DSETID_WLANREGS 0x00000028 /* override wlan regs */ -#define DSETID_STARTUP_PATCH2 0x00000029 - -#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */ - -/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */ -#define DSETID_INI_DATA 0x00000100 -/* Reserved for WHAL INI Tables: 0x100..0x11f */ -#define DSETID_INI_DATA_END 0x0000011f - -#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */ - -#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the - end of a memory-based - DataSet Index */ -#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */ - -/* - * PATCH DataSet format: - * A list of patches, terminated by a patch with - * address=PATCH_END. - * - * This allows for patches to be stored in flash. - */ -PREPACK struct patch_s { - u32 *address; - u32 data; -} POSTPACK ; - -/* - * Skip some patches. Can be used to erase a single patch in a - * patch DataSet without having to re-write the DataSet. May - * also be used to embed information for use by subsequent - * patch code. The "data" in a PATCH_SKIP tells how many - * bytes of length "patch_s" to skip. - */ -#define PATCH_SKIP ((u32 *)0x00000000) - -/* - * Execute code at the address specified by "data". - * The address of the patch structure is passed as - * the one parameter. - */ -#define PATCH_CODE_ABS ((u32 *)0x00000001) - -/* - * Same as PATCH_CODE_ABS, but treat "data" as an - * offset from the start of the patch word. - */ -#define PATCH_CODE_REL ((u32 *)0x00000002) - -/* Mark the end of this patch DataSet. */ -#define PATCH_END ((u32 *)0xffffffff) - -/* - * A DataSet which contains a Binary Patch to some other DataSet - * uses the original dsetid with the DSETID_BPATCH_FLAG bit set. - * Such a BPatch DataSet consists of BPatch metadata followed by - * the bdiff bytes. BPatch metadata consists of a single 32-bit - * word that contains the size of the BPatched final image. - * - * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff - * to create "diffs": - * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs - * Then add BPatch metadata to the start of "diffs". - * - * NB: There are some implementation-induced restrictions - * on which DataSets can be BPatched. - */ -#define DSETID_BPATCH_FLAG 0x80000000 - -#endif /* __DSETID_H__ */ diff --git a/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h b/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h deleted file mode 100644 index 4904040..0000000 --- a/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h +++ /dev/null @@ -1,237 +0,0 @@ -//------------------------------------------------------------------------------ -// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -//------------------------------------------------------------------------------ -//============================================================================== -// Author(s): ="Atheros" -//============================================================================== - -#ifndef __REG_DBSCHEMA_H__ -#define __REG_DBSCHEMA_H__ - -/* - * This file describes the regulatory DB schema, which is common between the - * 'generator' and 'parser'. The 'generator' runs on a host(typically a x86 - * Linux) and spits outs two binary files, which follow the DB file - * format(described below). The resultant output "regulatoryData_AG.bin" - * is binary file which has information regarding A and G regulatory - * information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory - * information. This binary file is parsed in the target for extracting - * regulatory information. - * - * The DB values used to populate the regulatory DB are defined in - * reg_dbvalues.h - * - */ - -/* Binary data file - Representation of Regulatory DB*/ -#define REG_DATA_FILE_AG "./regulatoryData_AG.bin" -#define REG_DATA_FILE_G "./regulatoryData_G.bin" - - -/* Table tags used to encode different tables in the database */ -enum data_tags_t{ - REG_DMN_PAIR_MAPPING_TAG = 0, - REG_COUNTRY_CODE_TO_ENUM_RD_TAG, - REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG, - REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG, - REG_DOMAIN_TAG, - MAX_DB_TABLE_TAGS - }; - - - -/* - **************************************************************************** - * Regulatory DB file format : - * 4-bytes : "RGDB" (Magic Key) - * 4-bytes : version (Default is 5379(my extn)) - * 4-bytes : length of file - * dbType(4) - * TAG(4) - * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... - * TAG(4) - * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... - * TAG(4) - * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data.... - * ... - * ... - **************************************************************************** - * - */ - -/* - * Length of the file would be filled in when the file is created and - * it would include the header size. - */ - -#define REG_DB_KEY "RGDB" /* Should be EXACTLY 4-bytes */ -#define REG_DB_VER 7802 /* Between 0-9999 */ -/* REG_DB_VER history in reverse chronological order: - * 7802: 78 (ASCII code of N) + 02 (minor version number) - updated 10/21/09 - * 7801: 78 (ASCII code of N) + 01 (minor version number, increment on further changes) - * 1178: '11N' = 11 + ASCII code of N(78) - * 5379: initial version, no 11N support - */ -#define MAGIC_KEY_OFFSET 0 -#define VERSION_OFFSET 4 -#define FILE_SZ_OFFSET 8 -#define DB_TYPE_OFFSET 12 - -#define MAGIC_KEY_SZ 4 -#define VERSION_SZ 4 -#define FILE_SZ_SZ 4 -#define DB_TYPE_SZ 4 -#define DB_TAG_SZ 4 - -#define REGDB_GET_MAGICKEY(x) ((char *)x + MAGIC_KEY_OFFSET) -#define REGDB_GET_VERSION(x) ((char *)x + VERSION_OFFSET) -#define REGDB_GET_FILESIZE(x) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) -#define REGDB_GET_DBTYPE(x) *((char *)x + DB_TYPE_OFFSET) - -#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_) -#define REGDB_IS_EOF(cur, begin) ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) ) - - -/* A Table can be search based on key as a parameter or accessed directly - * by giving its index in to the table. - */ -enum searchType { - KEY_BASED_TABLE_SEARCH = 1, - INDEX_BASED_TABLE_ACCESS - }; - - -/* Data is organised as different tables. There is a Master table, which - * holds information regarding all the tables. It does not have any - * knowledge about the attributes of the table it is holding - * but has external view of the same(for ex, how many entries, record size, - * how to search the table, total table size and reference to the data - * instance of table). - */ -typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structures */ - u8 numOfEntries; - char entrySize; /* Entry size per table row */ - char searchType; /* Index based access or key based */ - char reserved[3]; /* for alignment */ - u16 tableSize; /* Size of this table */ - char *dataPtr; /* Ptr to the actual Table */ -} POSTPACK dbMasterTable; /* Master table - table of tables */ - - -/* used to get the number of rows in a table */ -#define REGDB_NUM_OF_ROWS(a) (sizeof (a) / sizeof (a[0])) - -/* - * Used to set the RegDomain bitmask which chooses which frequency - * band specs are used. - */ - -#define BMLEN 2 /* Use 2 32-bit uint for channel bitmask */ -#define BMZERO {0,0} /* BMLEN zeros */ - -#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ - {((((_fa >= 0) && (_fa < 32)) ? (((u32) 1) << _fa) : 0) | \ - (((_fb >= 0) && (_fb < 32)) ? (((u32) 1) << _fb) : 0) | \ - (((_fc >= 0) && (_fc < 32)) ? (((u32) 1) << _fc) : 0) | \ - (((_fd >= 0) && (_fd < 32)) ? (((u32) 1) << _fd) : 0) | \ - (((_fe >= 0) && (_fe < 32)) ? (((u32) 1) << _fe) : 0) | \ - (((_ff >= 0) && (_ff < 32)) ? (((u32) 1) << _ff) : 0) | \ - (((_fg >= 0) && (_fg < 32)) ? (((u32) 1) << _fg) : 0) | \ - (((_fh >= 0) && (_fh < 32)) ? (((u32) 1) << _fh) : 0)), \ - ((((_fa > 31) && (_fa < 64)) ? (((u32) 1) << (_fa - 32)) : 0) | \ - (((_fb > 31) && (_fb < 64)) ? (((u32) 1) << (_fb - 32)) : 0) | \ - (((_fc > 31) && (_fc < 64)) ? (((u32) 1) << (_fc - 32)) : 0) | \ - (((_fd > 31) && (_fd < 64)) ? (((u32) 1) << (_fd - 32)) : 0) | \ - (((_fe > 31) && (_fe < 64)) ? (((u32) 1) << (_fe - 32)) : 0) | \ - (((_ff > 31) && (_ff < 64)) ? (((u32) 1) << (_ff - 32)) : 0) | \ - (((_fg > 31) && (_fg < 64)) ? (((u32) 1) << (_fg - 32)) : 0) | \ - (((_fh > 31) && (_fh < 64)) ? (((u32) 1) << (_fh - 32)) : 0))} - - -/* - * THE following table is the mapping of regdomain pairs specified by - * a regdomain value to the individual unitary reg domains - */ - -typedef PREPACK struct reg_dmn_pair_mapping { - u16 regDmnEnum; /* 16 bit reg domain pair */ - u16 regDmn5GHz; /* 5GHz reg domain */ - u16 regDmn2GHz; /* 2GHz reg domain */ - u8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */ - u8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */ - u32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan - flags. This value is used as a mask on the unitary flags*/ -} POSTPACK REG_DMN_PAIR_MAPPING; - -#define OFDM_YES (1 << 0) -#define OFDM_NO (0 << 0) -#define MCS_HT20_YES (1 << 1) -#define MCS_HT20_NO (0 << 1) -#define MCS_HT40_A_YES (1 << 2) -#define MCS_HT40_A_NO (0 << 2) -#define MCS_HT40_G_YES (1 << 3) -#define MCS_HT40_G_NO (0 << 3) - -typedef PREPACK struct { - u16 countryCode; - u16 regDmnEnum; - char isoName[3]; - char allowMode; /* what mode is allowed - bit 0: OFDM; bit 1: MCS_HT20; bit 2: MCS_HT40_A; bit 3: MCS_HT40_G */ -} POSTPACK COUNTRY_CODE_TO_ENUM_RD; - -/* lower 16 bits of ht40ChanMask */ -#define NO_FREQ_HT40 0x0 /* no freq is HT40 capable */ -#define F1_TO_F4_HT40 0xF /* freq 1 to 4 in the block is ht40 capable */ -#define F2_TO_F3_HT40 0x6 /* freq 2 to 3 in the block is ht40 capable */ -#define F1_TO_F10_HT40 0x3FF /* freq 1 to 10 in the block is ht40 capable */ -#define F3_TO_F11_HT40 0x7FC /* freq 3 to 11 in the block is ht40 capable */ -#define F3_TO_F9_HT40 0x1FC /* freq 3 to 9 in the block is ht40 capable */ -#define F1_TO_F8_HT40 0xFF /* freq 1 to 8 in the block is ht40 capable */ -#define F1_TO_F4_F9_TO_F10_HT40 0x30F /* freq 1 to 4, 9 to 10 in the block is ht40 capable */ - -/* upper 16 bits of ht40ChanMask */ -#define FREQ_HALF_RATE 0x10000 -#define FREQ_QUARTER_RATE 0x20000 - -typedef PREPACK struct RegDmnFreqBand { - u16 lowChannel; /* Low channel center in MHz */ - u16 highChannel; /* High Channel center in MHz */ - u8 power; /* Max power (dBm) for channel range */ - u8 channelSep; /* Channel separation within the band */ - u8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */ - u8 mode; /* Mode of operation */ - u32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */ - u32 ht40ChanMask; /* lower 16 bits: indicate which frequencies in the block is HT40 capable - upper 16 bits: what rate (half/quarter) the channel is */ -} POSTPACK REG_DMN_FREQ_BAND; - - - -typedef PREPACK struct regDomain { - u16 regDmnEnum; /* value from EnumRd table */ - u8 rdCTL; - u8 maxAntGain; - u8 dfsMask; /* DFS bitmask for 5Ghz tables */ - u8 flags; /* Requirement flags (AdHoc disallow etc) */ - u16 reserved; /* for alignment */ - u32 pscan; /* Bitmask for passive scan */ - u32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */ - u32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */ -} POSTPACK REG_DOMAIN; - -#endif /* __REG_DBSCHEMA_H__ */ diff --git a/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h b/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h deleted file mode 100644 index 278f903..0000000 --- a/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h +++ /dev/null @@ -1,504 +0,0 @@ -//------------------------------------------------------------------------------ -// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -//------------------------------------------------------------------------------ -//============================================================================== -// Author(s): ="Atheros" -//============================================================================== - - -#ifndef __REG_DBVALUE_H__ -#define __REG_DBVALUE_H__ - -/* - * Numbering from ISO 3166 - */ -enum CountryCode { - CTRY_ALBANIA = 8, /* Albania */ - CTRY_ALGERIA = 12, /* Algeria */ - CTRY_ARGENTINA = 32, /* Argentina */ - CTRY_ARMENIA = 51, /* Armenia */ - CTRY_ARUBA = 533, /* Aruba */ - CTRY_AUSTRALIA = 36, /* Australia (for STA) */ - CTRY_AUSTRALIA_AP = 5000, /* Australia (for AP) */ - CTRY_AUSTRIA = 40, /* Austria */ - CTRY_AZERBAIJAN = 31, /* Azerbaijan */ - CTRY_BAHRAIN = 48, /* Bahrain */ - CTRY_BANGLADESH = 50, /* Bangladesh */ - CTRY_BARBADOS = 52, /* Barbados */ - CTRY_BELARUS = 112, /* Belarus */ - CTRY_BELGIUM = 56, /* Belgium */ - CTRY_BELIZE = 84, /* Belize */ - CTRY_BOLIVIA = 68, /* Bolivia */ - CTRY_BOSNIA_HERZEGOWANIA = 70, /* Bosnia & Herzegowania */ - CTRY_BRAZIL = 76, /* Brazil */ - CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ - CTRY_BULGARIA = 100, /* Bulgaria */ - CTRY_CAMBODIA = 116, /* Cambodia */ - CTRY_CANADA = 124, /* Canada (for STA) */ - CTRY_CANADA_AP = 5001, /* Canada (for AP) */ - CTRY_CHILE = 152, /* Chile */ - CTRY_CHINA = 156, /* People's Republic of China */ - CTRY_COLOMBIA = 170, /* Colombia */ - CTRY_COSTA_RICA = 188, /* Costa Rica */ - CTRY_CROATIA = 191, /* Croatia */ - CTRY_CYPRUS = 196, - CTRY_CZECH = 203, /* Czech Republic */ - CTRY_DENMARK = 208, /* Denmark */ - CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ - CTRY_ECUADOR = 218, /* Ecuador */ - CTRY_EGYPT = 818, /* Egypt */ - CTRY_EL_SALVADOR = 222, /* El Salvador */ - CTRY_ESTONIA = 233, /* Estonia */ - CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ - CTRY_FINLAND = 246, /* Finland */ - CTRY_FRANCE = 250, /* France */ - CTRY_FRANCE2 = 255, /* France2 */ - CTRY_GEORGIA = 268, /* Georgia */ - CTRY_GERMANY = 276, /* Germany */ - CTRY_GREECE = 300, /* Greece */ - CTRY_GREENLAND = 304, /* Greenland */ - CTRY_GRENADA = 308, /* Grenada */ - CTRY_GUAM = 316, /* Guam */ - CTRY_GUATEMALA = 320, /* Guatemala */ - CTRY_HAITI = 332, /* Haiti */ - CTRY_HONDURAS = 340, /* Honduras */ - CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ - CTRY_HUNGARY = 348, /* Hungary */ - CTRY_ICELAND = 352, /* Iceland */ - CTRY_INDIA = 356, /* India */ - CTRY_INDONESIA = 360, /* Indonesia */ - CTRY_IRAN = 364, /* Iran */ - CTRY_IRAQ = 368, /* Iraq */ - CTRY_IRELAND = 372, /* Ireland */ - CTRY_ISRAEL = 376, /* Israel */ - CTRY_ITALY = 380, /* Italy */ - CTRY_JAMAICA = 388, /* Jamaica */ - CTRY_JAPAN = 392, /* Japan */ - CTRY_JAPAN1 = 393, /* Japan (JP1) */ - CTRY_JAPAN2 = 394, /* Japan (JP0) */ - CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ - CTRY_JAPAN4 = 396, /* Japan (JE1) */ - CTRY_JAPAN5 = 397, /* Japan (JE2) */ - CTRY_JAPAN6 = 399, /* Japan (JP6) */ - CTRY_JORDAN = 400, /* Jordan */ - CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ - CTRY_KENYA = 404, /* Kenya */ - CTRY_KOREA_NORTH = 408, /* North Korea */ - CTRY_KOREA_ROC = 410, /* South Korea (for STA) */ - CTRY_KOREA_ROC2 = 411, /* South Korea */ - CTRY_KOREA_ROC3 = 412, /* South Korea (for AP) */ - CTRY_KUWAIT = 414, /* Kuwait */ - CTRY_LATVIA = 428, /* Latvia */ - CTRY_LEBANON = 422, /* Lebanon */ - CTRY_LIBYA = 434, /* Libya */ - CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ - CTRY_LITHUANIA = 440, /* Lithuania */ - CTRY_LUXEMBOURG = 442, /* Luxembourg */ - CTRY_MACAU = 446, /* Macau */ - CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */ - CTRY_MALAYSIA = 458, /* Malaysia */ - CTRY_MALTA = 470, /* Malta */ - CTRY_MEXICO = 484, /* Mexico */ - CTRY_MONACO = 492, /* Principality of Monaco */ - CTRY_MOROCCO = 504, /* Morocco */ - CTRY_NEPAL = 524, /* Nepal */ - CTRY_NETHERLANDS = 528, /* Netherlands */ - CTRY_NETHERLAND_ANTILLES = 530, /* Netherlands-Antilles */ - CTRY_NEW_ZEALAND = 554, /* New Zealand */ - CTRY_NICARAGUA = 558, /* Nicaragua */ - CTRY_NORWAY = 578, /* Norway */ - CTRY_OMAN = 512, /* Oman */ - CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ - CTRY_PANAMA = 591, /* Panama */ - CTRY_PARAGUAY = 600, /* Paraguay */ - CTRY_PERU = 604, /* Peru */ - CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ - CTRY_POLAND = 616, /* Poland */ - CTRY_PORTUGAL = 620, /* Portugal */ - CTRY_PUERTO_RICO = 630, /* Puerto Rico */ - CTRY_QATAR = 634, /* Qatar */ - CTRY_ROMANIA = 642, /* Romania */ - CTRY_RUSSIA = 643, /* Russia */ - CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ - CTRY_MONTENEGRO = 891, /* Montenegro */ - CTRY_SINGAPORE = 702, /* Singapore */ - CTRY_SLOVAKIA = 703, /* Slovak Republic */ - CTRY_SLOVENIA = 705, /* Slovenia */ - CTRY_SOUTH_AFRICA = 710, /* South Africa */ - CTRY_SPAIN = 724, /* Spain */ - CTRY_SRILANKA = 144, /* Sri Lanka */ - CTRY_SWEDEN = 752, /* Sweden */ - CTRY_SWITZERLAND = 756, /* Switzerland */ - CTRY_SYRIA = 760, /* Syria */ - CTRY_TAIWAN = 158, /* Taiwan */ - CTRY_THAILAND = 764, /* Thailand */ - CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ - CTRY_TUNISIA = 788, /* Tunisia */ - CTRY_TURKEY = 792, /* Turkey */ - CTRY_UAE = 784, /* U.A.E. */ - CTRY_UKRAINE = 804, /* Ukraine */ - CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ - CTRY_UNITED_STATES = 840, /* United States (for STA) */ - CTRY_UNITED_STATES_AP = 841, /* United States (for AP) */ - CTRY_UNITED_STATES_PS = 842, /* United States - public safety */ - CTRY_URUGUAY = 858, /* Uruguay */ - CTRY_UZBEKISTAN = 860, /* Uzbekistan */ - CTRY_VENEZUELA = 862, /* Venezuela */ - CTRY_VIET_NAM = 704, /* Viet Nam */ - CTRY_YEMEN = 887, /* Yemen */ - CTRY_ZIMBABWE = 716 /* Zimbabwe */ -}; - -#define CTRY_DEBUG 0 -#define CTRY_DEFAULT 0x1ff - -/* - * The following regulatory domain definitions are - * found in the EEPROM. Each regulatory domain - * can operate in either a 5GHz or 2.4GHz wireless mode or - * both 5GHz and 2.4GHz wireless modes. - * In general, the value holds no special - * meaning and is used to decode into either specific - * 2.4GHz or 5GHz wireless mode for that particular - * regulatory domain. - * - * Enumerated Regulatory Domain Information 8 bit values indicate that - * the regdomain is really a pair of unitary regdomains. 12 bit values - * are the real unitary regdomains and are the only ones which have the - * frequency bitmasks and flags set. - */ - -enum EnumRd { - NO_ENUMRD = 0x00, - NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */ - NULL1_ETSIB = 0x07, /* Israel */ - NULL1_ETSIC = 0x08, - - FCC1_FCCA = 0x10, /* USA */ - FCC1_WORLD = 0x11, /* Hong Kong */ - FCC2_FCCA = 0x20, /* Canada */ - FCC2_WORLD = 0x21, /* Australia & HK */ - FCC2_ETSIC = 0x22, - FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */ - FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */ - FCC4_FCCA = 0x12, /* FCC public safety plus UNII bands */ - FCC5_FCCA = 0x13, /* US with no DFS */ - FCC5_WORLD = 0x16, /* US with no DFS */ - FCC6_FCCA = 0x14, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for US & Canada APs */ - FCC6_WORLD = 0x23, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for Australia APs */ - - ETSI1_WORLD = 0x37, - - ETSI2_WORLD = 0x35, /* Hungary & others */ - ETSI3_WORLD = 0x36, /* France & others */ - ETSI4_WORLD = 0x30, - ETSI4_ETSIC = 0x38, - ETSI5_WORLD = 0x39, - ETSI6_WORLD = 0x34, /* Bulgaria */ - ETSI_RESERVED = 0x33, /* Reserved (Do not used) */ - FRANCE_RES = 0x31, /* Legacy France for OEM */ - - APL6_WORLD = 0x5B, /* Singapore */ - APL4_WORLD = 0x42, /* Singapore */ - APL3_FCCA = 0x50, - APL_RESERVED = 0x44, /* Reserved (Do not used) */ - APL2_WORLD = 0x45, /* Korea */ - APL2_APLC = 0x46, - APL3_WORLD = 0x47, - APL2_APLD = 0x49, /* Korea with 2.3G channels */ - APL2_FCCA = 0x4D, /* Specific Mobile Customer */ - APL1_WORLD = 0x52, /* Latin America */ - APL1_FCCA = 0x53, - APL1_ETSIC = 0x55, - APL2_ETSIC = 0x56, /* Venezuela */ - APL5_WORLD = 0x58, /* Chile */ - APL7_FCCA = 0x5C, - APL8_WORLD = 0x5D, - APL9_WORLD = 0x5E, - APL10_WORLD = 0x5F, /* Korea 5GHz for STA */ - - - MKK5_MKKA = 0x99, /* This is a temporary value. MG and DQ have to give official one */ - MKK5_FCCA = 0x9A, /* This is a temporary value. MG and DQ have to give official one */ - MKK5_MKKC = 0x88, - MKK11_MKKA = 0xD4, - MKK11_FCCA = 0xD5, - MKK11_MKKC = 0xD7, - - /* - * World mode SKUs - */ - WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */ - WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */ - WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */ - WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */ - WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */ - WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */ - - WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */ - WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */ - EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */ - - WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */ - WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */ - WORB_WORLD = 0x6B, /* WorldB (WOA SKU) */ - WORC_WORLD = 0x6C, /* WorldC (WOA SKU) */ - - /* - * Regulator domains ending in a number (e.g. APL1, - * MK1, ETSI4, etc) apply to 5GHz channel and power - * information. Regulator domains ending in a letter - * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and - * power information. - */ - APL1 = 0x0150, /* LAT & Asia */ - APL2 = 0x0250, /* LAT & Asia */ - APL3 = 0x0350, /* Taiwan */ - APL4 = 0x0450, /* Jordan */ - APL5 = 0x0550, /* Chile */ - APL6 = 0x0650, /* Singapore */ - APL7 = 0x0750, /* Taiwan */ - APL8 = 0x0850, /* Malaysia */ - APL9 = 0x0950, /* Korea */ - APL10 = 0x1050, /* Korea 5GHz */ - - ETSI1 = 0x0130, /* Europe & others */ - ETSI2 = 0x0230, /* Europe & others */ - ETSI3 = 0x0330, /* Europe & others */ - ETSI4 = 0x0430, /* Europe & others */ - ETSI5 = 0x0530, /* Europe & others */ - ETSI6 = 0x0630, /* Europe & others */ - ETSIB = 0x0B30, /* Israel */ - ETSIC = 0x0C30, /* Latin America */ - - FCC1 = 0x0110, /* US & others */ - FCC2 = 0x0120, /* Canada, Australia & New Zealand */ - FCC3 = 0x0160, /* US w/new middle band & DFS */ - FCC4 = 0x0165, - FCC5 = 0x0180, - FCC6 = 0x0610, - FCCA = 0x0A10, - - APLD = 0x0D50, /* South Korea */ - - MKK1 = 0x0140, /* Japan */ - MKK2 = 0x0240, /* Japan Extended */ - MKK3 = 0x0340, /* Japan new 5GHz */ - MKK4 = 0x0440, /* Japan new 5GHz */ - MKK5 = 0x0540, /* Japan new 5GHz */ - MKK6 = 0x0640, /* Japan new 5GHz */ - MKK7 = 0x0740, /* Japan new 5GHz */ - MKK8 = 0x0840, /* Japan new 5GHz */ - MKK9 = 0x0940, /* Japan new 5GHz */ - MKK10 = 0x1040, /* Japan new 5GHz */ - MKK11 = 0x1140, /* Japan new 5GHz */ - MKK12 = 0x1240, /* Japan new 5GHz */ - - MKKA = 0x0A40, /* Japan */ - MKKC = 0x0A50, - - NULL1 = 0x0198, - WORLD = 0x0199, - DEBUG_REG_DMN = 0x01ff, - UNINIT_REG_DMN = 0x0fff, -}; - -enum { /* conformance test limits */ - FCC = 0x10, - MKK = 0x40, - ETSI = 0x30, - NO_CTL = 0xff, - CTL_11B = 1, - CTL_11G = 2 -}; - - -/* - * The following are flags for different requirements per reg domain. - * These requirements are either inhereted from the reg domain pair or - * from the unitary reg domain if the reg domain pair flags value is - * 0 - */ - -enum { - NO_REQ = 0x00, - DISALLOW_ADHOC_11A = 0x01, - ADHOC_PER_11D = 0x02, - ADHOC_NO_11A = 0x04, - DISALLOW_ADHOC_11G = 0x08 -}; - - - - -/* - * The following describe the bit masks for different passive scan - * capability/requirements per regdomain. - */ -#define NO_PSCAN 0x00000000 -#define PSCAN_FCC 0x00000001 -#define PSCAN_ETSI 0x00000002 -#define PSCAN_MKK 0x00000004 -#define PSCAN_ETSIB 0x00000008 -#define PSCAN_ETSIC 0x00000010 -#define PSCAN_WWR 0x00000020 -#define PSCAN_DEFER 0xFFFFFFFF - -/* Bit masks for DFS per regdomain */ - -enum { - NO_DFS = 0x00, - DFS_FCC3 = 0x01, - DFS_ETSI = 0x02, - DFS_MKK = 0x04 -}; - - -#define DEF_REGDMN FCC1_FCCA - -/* - * The following table is the master list for all different freqeuncy - * bands with the complete matrix of all possible flags and settings - * for each band if it is used in ANY reg domain. - * - * The table of frequency bands is indexed by a bitmask. The ordering - * must be consistent with the enum below. When adding a new - * frequency band, be sure to match the location in the enum with the - * comments - */ - -/* - * These frequency values are as per channel tags and regulatory domain - * info. Please update them as database is updated. - */ -#define A_FREQ_MIN 4920 -#define A_FREQ_MAX 5825 - -#define A_CHAN0_FREQ 5000 -#define A_CHAN_MAX ((A_FREQ_MAX - A_CHAN0_FREQ)/5) - -#define BG_FREQ_MIN 2412 -#define BG_FREQ_MAX 2484 - -#define BG_CHAN0_FREQ 2407 -#define BG_CHAN_MIN ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5) -#define BG_CHAN_MAX 14 /* corresponding to 2484 MHz */ - -#define A_20MHZ_BAND_FREQ_MAX 5000 - - -/* - * 5GHz 11A channel tags - */ - -enum { - F1_4920_4980, - F1_5040_5080, - - F1_5120_5240, - - F1_5180_5240, - F2_5180_5240, - F3_5180_5240, - F4_5180_5240, - F5_5180_5240, - F6_5180_5240, - F7_5180_5240, - - F1_5260_5280, - - F1_5260_5320, - F2_5260_5320, - F3_5260_5320, - F4_5260_5320, - F5_5260_5320, - F6_5260_5320, - - F1_5260_5700, - - F1_5280_5320, - - F1_5500_5620, - - F1_5500_5700, - F2_5500_5700, - F3_5500_5700, - F4_5500_5700, - F5_5500_5700, - F6_5500_5700, - F7_5500_5700, - - F1_5745_5805, - F2_5745_5805, - - F1_5745_5825, - F2_5745_5825, - F3_5745_5825, - F4_5745_5825, - F5_5745_5825, - F6_5745_5825, - - W1_4920_4980, - W1_5040_5080, - W1_5170_5230, - W1_5180_5240, - W1_5260_5320, - W1_5745_5825, - W1_5500_5700, -}; - - -/* 2.4 GHz table - for 11b and 11g info */ -enum { - BG1_2312_2372, - BG2_2312_2372, - - BG1_2412_2472, - BG2_2412_2472, - BG3_2412_2472, - BG4_2412_2472, - - BG1_2412_2462, - BG2_2412_2462, - - BG1_2432_2442, - - BG1_2457_2472, - - BG1_2467_2472, - - BG1_2484_2484, /* No G */ - BG2_2484_2484, /* No G */ - - BG1_2512_2732, - - WBG1_2312_2372, - WBG1_2412_2412, - WBG1_2417_2432, - WBG1_2437_2442, - WBG1_2447_2457, - WBG1_2462_2462, - WBG1_2467_2467, - WBG2_2467_2467, - WBG1_2472_2472, - WBG2_2472_2472, - WBG1_2484_2484, /* No G */ - WBG2_2484_2484, /* No G */ -}; - -#endif /* __REG_DBVALUE_H__ */ diff --git a/drivers/staging/ath6kl/include/common/wmi_thin.h b/drivers/staging/ath6kl/include/common/wmi_thin.h deleted file mode 100644 index 0a8364c..0000000 --- a/drivers/staging/ath6kl/include/common/wmi_thin.h +++ /dev/null @@ -1,347 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -//------------------------------------------------------------------------------ -//============================================================================== -// Author(s): ="Atheros" -//============================================================================== - -/* - * This file contains the definitions of the WMI protocol specified in the - * Wireless Module Interface (WMI). It includes definitions of all the - * commands and events. Commands are messages from the host to the WM. - * Events and Replies are messages from the WM to the host. - * - * Ownership of correctness in regards to WMI commands - * belongs to the host driver and the WM is not required to validate - * parameters for value, proper range, or any other checking. - * - */ - -#ifndef _WMI_THIN_H_ -#define _WMI_THIN_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef enum { - WMI_THIN_CONFIG_CMDID = 0x8000, // WMI_THIN_RESERVED_START - WMI_THIN_SET_MIB_CMDID, - WMI_THIN_GET_MIB_CMDID, - WMI_THIN_JOIN_CMDID, - /* add new CMDID's here */ - WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END -} WMI_THIN_COMMAND_ID; - -typedef enum{ - TEMPLATE_FRM_FIRST = 0, - TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST, - TEMPLATE_FRM_BEACON, - TEMPLATE_FRM_PROBE_RESP, - TEMPLATE_FRM_NULL, - TEMPLATE_FRM_QOS_NULL, - TEMPLATE_FRM_PSPOLL, - TEMPLATE_FRM_MAX -}WMI_TEMPLATE_FRM_TYPE; - -/* TEMPLATE_FRM_LEN... represent the maximum allowable - * data lengths (bytes) for each frame type */ -#define TEMPLATE_FRM_LEN_PROBE_REQ (256) /* Symbian dictates a minimum of 256 for these 3 frame types */ -#define TEMPLATE_FRM_LEN_BEACON (256) -#define TEMPLATE_FRM_LEN_PROBE_RESP (256) -#define TEMPLATE_FRM_LEN_NULL (32) -#define TEMPLATE_FRM_LEN_QOS_NULL (32) -#define TEMPLATE_FRM_LEN_PSPOLL (32) -#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \ - TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL) - - -/* MAC Header Build Rules */ -/* These values allow the host to configure the - * target code that is responsible for constructing - * the MAC header. In cases where the MAC header - * is provided by the host framework, the target - * has a diminished responsibility over what fields - * it must write. This will vary from framework to framework. - * Symbian requires different behavior from MAC80211 which - * requires different behavior from MS Native Wifi. */ -#define WMI_WRT_VER_TYPE 0x00000001 -#define WMI_WRT_DURATION 0x00000002 -#define WMI_WRT_DIRECTION 0x00000004 -#define WMI_WRT_POWER 0x00000008 -#define WMI_WRT_WEP 0x00000010 -#define WMI_WRT_MORE 0x00000020 -#define WMI_WRT_BSSID 0x00000040 -#define WMI_WRT_QOS 0x00000080 -#define WMI_WRT_SEQNO 0x00000100 -#define WMI_GUARD_TX 0x00000200 /* prevents TX ops that are not allowed for a current state */ -#define WMI_WRT_DEFAULT_CONFIG (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \ - WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \ - WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX) - -/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for - * TX Complete messages the will come from the Target. these messages are - * disabled by default but can be enabled using this structure and the - * WMI_THIN_CONFIG_CMDID. */ -typedef PREPACK struct { - u8 version; /* the versioned type of messages to use or 0 to disable */ - u8 countThreshold; /* msg count threshold triggering a tx complete message */ - u16 timeThreshold; /* timeout interval in MSEC triggering a tx complete message */ -} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE; - -/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames - * that have decryption errors. The default behavior is to discard the frame - * without notification. Alternately, the MAC Header is forwarded to the host - * with the failed status. */ -typedef PREPACK struct { - u8 enable; /* 1 == send decrypt errors to the host, 0 == don't */ - u8 reserved[3]; /* align padding */ -} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR; - -/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted - * frames that require partial MAC header construction. These rules - * are used by the target to indicate which fields need to be written. */ -typedef PREPACK struct { - u32 rules; /* combination of WMI_WRT_... values */ -} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES; - -/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received - * frames as to which frames should get forwarded to the host and which - * should get processed internally. */ -typedef PREPACK struct { - u32 rules; /* combination of WMI_FILT_... values */ -} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES; - -/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above - * WMI_THIN_CONFIG_... structures. The actual combination is indicated - * by the value of cfgField. Each bit in this field corresponds to - * one of the above structures. */ -typedef PREPACK struct { -#define WMI_THIN_CFG_TXCOMP 0x00000001 -#define WMI_THIN_CFG_DECRYPT 0x00000002 -#define WMI_THIN_CFG_MAC_RULES 0x00000004 -#define WMI_THIN_CFG_FILTER_RULES 0x00000008 - u32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */ - u16 length; /* length in bytes of appended sub-commands */ - u8 reserved[2]; /* align padding */ -} POSTPACK WMI_THIN_CONFIG_CMD; - -/* MIB Access Identifiers tailored for Symbian. */ -enum { - MIB_ID_STA_MAC = 1, // [READONLY] - MIB_ID_RX_LIFE_TIME, // [NOT IMPLEMENTED] - MIB_ID_SLOT_TIME, // [READ/WRITE] - MIB_ID_RTS_THRESHOLD, // [READ/WRITE] - MIB_ID_CTS_TO_SELF, // [READ/WRITE] - MIB_ID_TEMPLATE_FRAME, // [WRITE ONLY] - MIB_ID_RXFRAME_FILTER, // [READ/WRITE] - MIB_ID_BEACON_FILTER_TABLE, // [WRITE ONLY] - MIB_ID_BEACON_FILTER, // [READ/WRITE] - MIB_ID_BEACON_LOST_COUNT, // [WRITE ONLY] - MIB_ID_RSSI_THRESHOLD, // [WRITE ONLY] - MIB_ID_HT_CAP, // [NOT IMPLEMENTED] - MIB_ID_HT_OP, // [NOT IMPLEMENTED] - MIB_ID_HT_2ND_BEACON, // [NOT IMPLEMENTED] - MIB_ID_HT_BLOCK_ACK, // [NOT IMPLEMENTED] - MIB_ID_PREAMBLE, // [READ/WRITE] - /*MIB_ID_GROUP_ADDR_TABLE,*/ - /*MIB_ID_WEP_DEFAULT_KEY_ID */ - /*MIB_ID_TX_POWER */ - /*MIB_ID_ARP_IP_TABLE */ - /*MIB_ID_SLEEP_MODE */ - /*MIB_ID_WAKE_INTERVAL*/ - /*MIB_ID_STAT_TABLE*/ - /*MIB_ID_IBSS_PWR_SAVE*/ - /*MIB_ID_COUNTERS_TABLE*/ - /*MIB_ID_ETHERTYPE_FILTER*/ - /*MIB_ID_BC_UDP_FILTER*/ - -}; - -typedef PREPACK struct { - u8 addr[ATH_MAC_LEN]; -} POSTPACK WMI_THIN_MIB_STA_MAC; - -typedef PREPACK struct { - u32 time; // units == msec -} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME; - -typedef PREPACK struct { - u8 enable; //1 = on, 0 = off -} POSTPACK WMI_THIN_MIB_CTS_TO_SELF; - -typedef PREPACK struct { - u32 time; // units == usec -} POSTPACK WMI_THIN_MIB_SLOT_TIME; - -typedef PREPACK struct { - u16 length; //units == bytes -} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD; - -typedef PREPACK struct { - u8 type; // type of frame - u8 rate; // tx rate to be used (one of WMI_BIT_RATE) - u16 length; // num bytes following this structure as the template data -} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME; - -typedef PREPACK struct { -#define FRAME_FILTER_PROMISCUOUS 0x00000001 -#define FRAME_FILTER_BSSID 0x00000002 - u32 filterMask; -} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER; - - -#define IE_FILTER_TREATMENT_CHANGE 1 -#define IE_FILTER_TREATMENT_APPEAR 2 - -typedef PREPACK struct { - u8 ie; - u8 treatment; -} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE; - -typedef PREPACK struct { - u8 ie; - u8 treatment; - u8 oui[3]; - u8 type; - u16 version; -} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI; - -typedef PREPACK struct { - u16 numElements; - u8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4 - u8 reserved; -} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER; - -typedef PREPACK struct { - u32 count; /* num beacons between deliveries */ - u8 enable; - u8 reserved[3]; -} POSTPACK WMI_THIN_MIB_BEACON_FILTER; - -typedef PREPACK struct { - u32 count; /* num consec lost beacons after which send event */ -} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT; - -typedef PREPACK struct { - u8 rssi; /* the low threshold which can trigger an event warning */ - u8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */ - u8 count; /* the sample count of consecutive frames necessary to trigger an event. */ - u8 reserved[1]; /* padding */ -} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD; - - -typedef PREPACK struct { - u32 cap; - u32 rxRateField; - u32 beamForming; - u8 addr[ATH_MAC_LEN]; - u8 enable; - u8 stbc; - u8 maxAMPDU; - u8 msduSpacing; - u8 mcsFeedback; - u8 antennaSelCap; -} POSTPACK WMI_THIN_MIB_HT_CAP; - -typedef PREPACK struct { - u32 infoField; - u32 basicRateField; - u8 protection; - u8 secondChanneloffset; - u8 channelWidth; - u8 reserved; -} POSTPACK WMI_THIN_MIB_HT_OP; - -typedef PREPACK struct { -#define SECOND_BEACON_PRIMARY 1 -#define SECOND_BEACON_EITHER 2 -#define SECOND_BEACON_SECONDARY 3 - u8 cfg; - u8 reserved[3]; /* padding */ -} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON; - -typedef PREPACK struct { - u8 txTIDField; - u8 rxTIDField; - u8 reserved[2]; /* padding */ -} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK; - -typedef PREPACK struct { - u8 enableLong; // 1 == long preamble, 0 == short preamble - u8 reserved[3]; -} POSTPACK WMI_THIN_MIB_PREAMBLE; - -typedef PREPACK struct { - u16 length; /* the length in bytes of the appended MIB data */ - u8 mibID; /* the ID of the MIB element being set */ - u8 reserved; /* align padding */ -} POSTPACK WMI_THIN_SET_MIB_CMD; - -typedef PREPACK struct { - u8 mibID; /* the ID of the MIB element being set */ - u8 reserved[3]; /* align padding */ -} POSTPACK WMI_THIN_GET_MIB_CMD; - -typedef PREPACK struct { - u32 basicRateMask; /* bit mask of basic rates */ - u32 beaconIntval; /* TUs */ - u16 atimWindow; /* TUs */ - u16 channel; /* frequency in Mhz */ - u8 networkType; /* INFRA_NETWORK | ADHOC_NETWORK */ - u8 ssidLength; /* 0 - 32 */ - u8 probe; /* != 0 : issue probe req at start */ - u8 reserved; /* alignment */ - u8 ssid[WMI_MAX_SSID_LEN]; - u8 bssid[ATH_MAC_LEN]; -} POSTPACK WMI_THIN_JOIN_CMD; - -typedef PREPACK struct { - u16 dtim; /* dtim interval in num beacons */ - u16 aid; /* 80211 AID from Assoc resp */ -} POSTPACK WMI_THIN_POST_ASSOC_CMD; - -typedef enum { - WMI_THIN_EVENTID_RESERVED_START = 0x8000, - WMI_THIN_GET_MIB_EVENTID, - WMI_THIN_JOIN_EVENTID, - - /* Add new THIN EVENTID's here */ - WMI_THIN_EVENTID_RESERVED_END = 0x8fff -} WMI_THIN_EVENT_ID; - -/* Possible values for WMI_THIN_JOIN_EVENT.result */ -typedef enum { - WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network - WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason - WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit - WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param. -}WMI_THIN_JOIN_RESULT; - -typedef PREPACK struct { - u8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */ - u8 reserved[3]; /* alignment */ -} POSTPACK WMI_THIN_JOIN_EVENT; - -#ifdef __cplusplus -} -#endif - -#endif /* _WMI_THIN_H_ */ diff --git a/drivers/staging/ath6kl/include/target_reg_table.h b/drivers/staging/ath6kl/include/target_reg_table.h deleted file mode 100644 index e2225d5..0000000 --- a/drivers/staging/ath6kl/include/target_reg_table.h +++ /dev/null @@ -1,244 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -//------------------------------------------------------------------------------ -//============================================================================== -// Target register table macros and structure definitions -// -// Author(s): ="Atheros" -//============================================================================== - -#ifndef TARGET_REG_TABLE_H_ -#define TARGET_REG_TABLE_H_ - -#include "targaddrs.h" - -/*** WARNING : Add to the end of the TABLE! do not change the order ****/ -typedef struct targetdef_s { - u32 d_RTC_BASE_ADDRESS; - u32 d_SYSTEM_SLEEP_OFFSET; - u32 d_SYSTEM_SLEEP_DISABLE_LSB; - u32 d_SYSTEM_SLEEP_DISABLE_MASK; - u32 d_CLOCK_CONTROL_OFFSET; - u32 d_CLOCK_CONTROL_SI0_CLK_MASK; - u32 d_RESET_CONTROL_OFFSET; - u32 d_RESET_CONTROL_SI0_RST_MASK; - u32 d_GPIO_BASE_ADDRESS; - u32 d_GPIO_PIN0_OFFSET; - u32 d_GPIO_PIN1_OFFSET; - u32 d_GPIO_PIN0_CONFIG_MASK; - u32 d_GPIO_PIN1_CONFIG_MASK; - u32 d_SI_CONFIG_BIDIR_OD_DATA_LSB; - u32 d_SI_CONFIG_BIDIR_OD_DATA_MASK; - u32 d_SI_CONFIG_I2C_LSB; - u32 d_SI_CONFIG_I2C_MASK; - u32 d_SI_CONFIG_POS_SAMPLE_LSB; - u32 d_SI_CONFIG_POS_SAMPLE_MASK; - u32 d_SI_CONFIG_INACTIVE_CLK_LSB; - u32 d_SI_CONFIG_INACTIVE_CLK_MASK; - u32 d_SI_CONFIG_INACTIVE_DATA_LSB; - u32 d_SI_CONFIG_INACTIVE_DATA_MASK; - u32 d_SI_CONFIG_DIVIDER_LSB; - u32 d_SI_CONFIG_DIVIDER_MASK; - u32 d_SI_BASE_ADDRESS; - u32 d_SI_CONFIG_OFFSET; - u32 d_SI_TX_DATA0_OFFSET; - u32 d_SI_TX_DATA1_OFFSET; - u32 d_SI_RX_DATA0_OFFSET; - u32 d_SI_RX_DATA1_OFFSET; - u32 d_SI_CS_OFFSET; - u32 d_SI_CS_DONE_ERR_MASK; - u32 d_SI_CS_DONE_INT_MASK; - u32 d_SI_CS_START_LSB; - u32 d_SI_CS_START_MASK; - u32 d_SI_CS_RX_CNT_LSB; - u32 d_SI_CS_RX_CNT_MASK; - u32 d_SI_CS_TX_CNT_LSB; - u32 d_SI_CS_TX_CNT_MASK; - u32 d_BOARD_DATA_SZ; - u32 d_BOARD_EXT_DATA_SZ; -} TARGET_REGISTER_TABLE; - -#define BOARD_DATA_SZ_MAX 2048 - -#if defined(MY_TARGET_DEF) /* { */ - -#ifdef ATH_REG_TABLE_DIRECT_ASSIGN - -static struct targetdef_s my_target_def = { - RTC_BASE_ADDRESS, - SYSTEM_SLEEP_OFFSET, - SYSTEM_SLEEP_DISABLE_LSB, - SYSTEM_SLEEP_DISABLE_MASK, - CLOCK_CONTROL_OFFSET, - CLOCK_CONTROL_SI0_CLK_MASK, - RESET_CONTROL_OFFSET, - RESET_CONTROL_SI0_RST_MASK, - GPIO_BASE_ADDRESS, - GPIO_PIN0_OFFSET, - GPIO_PIN0_CONFIG_MASK, - GPIO_PIN1_OFFSET, - GPIO_PIN1_CONFIG_MASK, - SI_CONFIG_BIDIR_OD_DATA_LSB, - SI_CONFIG_BIDIR_OD_DATA_MASK, - SI_CONFIG_I2C_LSB, - SI_CONFIG_I2C_MASK, - SI_CONFIG_POS_SAMPLE_LSB, - SI_CONFIG_POS_SAMPLE_MASK, - SI_CONFIG_INACTIVE_CLK_LSB, - SI_CONFIG_INACTIVE_CLK_MASK, - SI_CONFIG_INACTIVE_DATA_LSB, - SI_CONFIG_INACTIVE_DATA_MASK, - SI_CONFIG_DIVIDER_LSB, - SI_CONFIG_DIVIDER_MASK, - SI_BASE_ADDRESS, - SI_CONFIG_OFFSET, - SI_TX_DATA0_OFFSET, - SI_TX_DATA1_OFFSET, - SI_RX_DATA0_OFFSET, - SI_RX_DATA1_OFFSET, - SI_CS_OFFSET, - SI_CS_DONE_ERR_MASK, - SI_CS_DONE_INT_MASK, - SI_CS_START_LSB, - SI_CS_START_MASK, - SI_CS_RX_CNT_LSB, - SI_CS_RX_CNT_MASK, - SI_CS_TX_CNT_LSB, - SI_CS_TX_CNT_MASK, - MY_TARGET_BOARD_DATA_SZ, - MY_TARGET_BOARD_EXT_DATA_SZ, -}; - -#else - -static struct targetdef_s my_target_def = { - .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS, - .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET, - .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB, - .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK, - .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET, - .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK, - .d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET, - .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK, - .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS, - .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET, - .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK, - .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET, - .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK, - .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB, - .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK, - .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB, - .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK, - .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB, - .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK, - .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB, - .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK, - .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB, - .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK, - .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB, - .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK, - .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS, - .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET, - .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET, - .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET, - .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET, - .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET, - .d_SI_CS_OFFSET = SI_CS_OFFSET, - .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK, - .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK, - .d_SI_CS_START_LSB = SI_CS_START_LSB, - .d_SI_CS_START_MASK = SI_CS_START_MASK, - .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB, - .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK, - .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB, - .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK, - .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ, - .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ, -}; - -#endif - -#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX -#error "BOARD_DATA_SZ_MAX is too small" -#endif - -struct targetdef_s *MY_TARGET_DEF = &my_target_def; - -#else /* } { */ - -#define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS) -#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET) -#define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB) -#define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK) -#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET) -#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) -#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET) -#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK) -#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS) -#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET) -#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK) -#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET) -#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK) -#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) -#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) -#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB) -#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK) -#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) -#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) -#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) -#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) -#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) -#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) -#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB) -#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK) -#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS) -#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET) -#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET) -#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET) -#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET) -#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET) -#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET) -#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK) -#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK) -#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB) -#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK) -#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB) -#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK) -#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB) -#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK) -#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ) -#define EEPROM_EXT_SZ (targetdef->d_BOARD_EXT_DATA_SZ) - -/* SET macros */ -#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) -#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) -#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) -#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) -#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) -#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) -#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) -#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) -#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) -#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) - -#endif /* } */ - -#endif /*TARGET_REG_TABLE_H_*/ - -