From patchwork Thu Aug 30 21:04:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gertjan van Wingerde X-Patchwork-Id: 1389661 Return-Path: X-Original-To: patchwork-linux-wireless@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 3DED6DF264 for ; Thu, 30 Aug 2012 21:04:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752609Ab2H3VEh (ORCPT ); Thu, 30 Aug 2012 17:04:37 -0400 Received: from cpsmtpb-ews01.kpnxchange.com ([213.75.39.4]:2561 "EHLO cpsmtpb-ews01.kpnxchange.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752516Ab2H3VEf (ORCPT ); Thu, 30 Aug 2012 17:04:35 -0400 Received: from cpsps-ews21.kpnxchange.com ([10.94.84.187]) by cpsmtpb-ews01.kpnxchange.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 30 Aug 2012 23:04:34 +0200 Received: from CPSMTPM-CMT104.kpnxchange.com ([195.121.3.20]) by cpsps-ews21.kpnxchange.com with Microsoft SMTPSVC(7.5.7601.17514); Thu, 30 Aug 2012 23:04:34 +0200 Received: from wingerd.gvw.nl ([86.87.118.224]) by CPSMTPM-CMT104.kpnxchange.com with Microsoft SMTPSVC(7.0.6002.18264); Thu, 30 Aug 2012 23:04:33 +0200 Received: by wingerd.gvw.nl (Postfix, from userid 1026) id 7BA0E202BF3; Thu, 30 Aug 2012 23:04:33 +0200 (CEST) From: Gertjan van Wingerde To: , "John W. Linville" Cc: , Ivo van Doorn , Helmut Schaa , Gertjan van Wingerde , Subject: [PATCH 11/17] rt2x00: Align rt61pci MAC_CSR13 definition with datasheet. Date: Thu, 30 Aug 2012 23:04:20 +0200 Message-Id: <1346360670-6498-3-git-send-email-gwingerde@gmail.com> X-Mailer: git-send-email 1.7.11.1 In-Reply-To: <1346360670-6498-2-git-send-email-gwingerde@gmail.com> References: <1346355248-5331-10-git-send-email-gwingerde@gmail.com> <1346360670-6498-1-git-send-email-gwingerde@gmail.com> <1346360670-6498-2-git-send-email-gwingerde@gmail.com> X-OriginalArrivalTime: 30 Aug 2012 21:04:33.0762 (UTC) FILETIME=[0E3C4C20:01CD86F3] Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Rename MAC_CSR13_BIT to MAC_CSR13_VAL and MAC_CSR13_DIR to represent the actual meaning better. Clean up list to only mention the active GPIO pins, not just all bits. Signed-off-by: Gertjan van Wingerde Cc: diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c index 3f7bc5c..d84b17f 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.c +++ b/drivers/net/wireless/rt2x00/rt61pci.c @@ -243,7 +243,7 @@ static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) u32 reg; rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); - return rt2x00_get_field32(reg, MAC_CSR13_BIT5); + return rt2x00_get_field32(reg, MAC_CSR13_VAL5); } #ifdef CONFIG_RT2X00_LIB_LEDS @@ -715,11 +715,11 @@ static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); - rt2x00_set_field32(®, MAC_CSR13_BIT4, p1); - rt2x00_set_field32(®, MAC_CSR13_BIT12, 0); + rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); + rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); - rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2); - rt2x00_set_field32(®, MAC_CSR13_BIT11, 0); + rt2x00_set_field32(®, MAC_CSR13_DIR3, 0); + rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2); rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg); } diff --git a/drivers/net/wireless/rt2x00/rt61pci.h b/drivers/net/wireless/rt2x00/rt61pci.h index e3cd6db..9bc6b60 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.h +++ b/drivers/net/wireless/rt2x00/rt61pci.h @@ -357,21 +357,22 @@ struct hw_pairwise_ta_entry { /* * MAC_CSR13: GPIO. + * MAC_CSR13_VALx: GPIO value + * MAC_CSR13_DIRx: GPIO direction: 0 = output; 1 = input */ #define MAC_CSR13 0x3034 -#define MAC_CSR13_BIT0 FIELD32(0x00000001) -#define MAC_CSR13_BIT1 FIELD32(0x00000002) -#define MAC_CSR13_BIT2 FIELD32(0x00000004) -#define MAC_CSR13_BIT3 FIELD32(0x00000008) -#define MAC_CSR13_BIT4 FIELD32(0x00000010) -#define MAC_CSR13_BIT5 FIELD32(0x00000020) -#define MAC_CSR13_BIT6 FIELD32(0x00000040) -#define MAC_CSR13_BIT7 FIELD32(0x00000080) -#define MAC_CSR13_BIT8 FIELD32(0x00000100) -#define MAC_CSR13_BIT9 FIELD32(0x00000200) -#define MAC_CSR13_BIT10 FIELD32(0x00000400) -#define MAC_CSR13_BIT11 FIELD32(0x00000800) -#define MAC_CSR13_BIT12 FIELD32(0x00001000) +#define MAC_CSR13_VAL0 FIELD32(0x00000001) +#define MAC_CSR13_VAL1 FIELD32(0x00000002) +#define MAC_CSR13_VAL2 FIELD32(0x00000004) +#define MAC_CSR13_VAL3 FIELD32(0x00000008) +#define MAC_CSR13_VAL4 FIELD32(0x00000010) +#define MAC_CSR13_VAL5 FIELD32(0x00000020) +#define MAC_CSR13_DIR0 FIELD32(0x00000100) +#define MAC_CSR13_DIR1 FIELD32(0x00000200) +#define MAC_CSR13_DIR2 FIELD32(0x00000400) +#define MAC_CSR13_DIR3 FIELD32(0x00000800) +#define MAC_CSR13_DIR4 FIELD32(0x00001000) +#define MAC_CSR13_DIR5 FIELD32(0x00002000) /* * MAC_CSR14: LED control register.