From patchwork Mon Oct 15 08:01:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manoharan, Rajkumar" X-Patchwork-Id: 1592741 Return-Path: X-Original-To: patchwork-linux-wireless@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id D7ABE3FD86 for ; Mon, 15 Oct 2012 08:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751211Ab2JOITJ (ORCPT ); Mon, 15 Oct 2012 04:19:09 -0400 Received: from wolverine02.qualcomm.com ([199.106.114.251]:36888 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751039Ab2JOITI (ORCPT ); Mon, 15 Oct 2012 04:19:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=qca.qualcomm.com; i=@qca.qualcomm.com; q=dns/txt; s=qcdkim; t=1350289148; x=1381825148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=QRPDyTLF09ESx2C4QdwFnAprdf2aKNdhUQM9+fTXKy8=; b=upP+XOoRJVe3ogp/UQDUX9DOQTIhbN/ABMVN6ZXhHYzp8pfwwgFxDhr3 Cu7b836qee7pU+KIkfh2I4LxWF0Bu6pVOuWB1vT7MzeHY9/QvAJPJOhSY /oRCac+7kMb7nIj00/wNhP7am/wfL9uFEKSwsFUPCA6Wy3aD7Z3EzETb0 M=; X-IronPort-AV: E=McAfee;i="5400,1158,6865"; a="248609703" Received: from ironmsg03-l.qualcomm.com ([172.30.48.18]) by wolverine02.qualcomm.com with ESMTP; 15 Oct 2012 01:01:50 -0700 X-IronPort-AV: E=Sophos;i="4.80,587,1344236400"; d="scan'208";a="347172887" Received: from nasanexhc07.na.qualcomm.com ([172.30.39.190]) by Ironmsg03-L.qualcomm.com with ESMTP/TLS/RC4-SHA; 15 Oct 2012 01:01:50 -0700 Received: from qcmail1.qualcomm.com (172.30.39.5) by qcmail1.qualcomm.com (172.30.39.190) with Microsoft SMTP Server (TLS) id 14.2.318.1; Mon, 15 Oct 2012 01:01:48 -0700 Received: by qcmail1.qualcomm.com (sSMTP sendmail emulation); Mon, 15 Oct 2012 13:31:48 +0530 From: Rajkumar Manoharan To: CC: , Rajkumar Manoharan , Bala Shanmugam Subject: [PATCH 04/12] ath9k: turn off RXIQ calibration while re-calibrating radio Date: Mon, 15 Oct 2012 13:31:29 +0530 Message-ID: <1350288089-18808-2-git-send-email-rmanohar@qca.qualcomm.com> X-Mailer: git-send-email 1.7.12.2 In-Reply-To: <1350288089-18808-1-git-send-email-rmanohar@qca.qualcomm.com> References: <1350288089-18808-1-git-send-email-rmanohar@qca.qualcomm.com> MIME-Version: 1.0 X-Originating-IP: [172.30.39.5] Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Bala Shanmugam TXIQ and RXIQ share the same data path to upload the measurement result, we should turn off RXIQ calibration while re-calibrating radio Signed-off-by: Bala Shanmugam --- drivers/net/wireless/ath/ath9k/ar9003_mci.c | 6 ++++++ drivers/net/wireless/ath/ath9k/ar9003_phy.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.c b/drivers/net/wireless/ath/ath9k/ar9003_mci.c index b2b9941..c46d8f1 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mci.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.c @@ -750,6 +750,9 @@ int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, mci_hw->bt_state = MCI_BT_AWAKE; + REG_CLR_BIT(ah, AR_PHY_TIMING4, + 1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT); + if (caldata) { caldata->done_txiqcal_once = false; caldata->done_txclcal_once = false; @@ -759,6 +762,9 @@ int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, if (!ath9k_hw_init_cal(ah, chan)) return -EIO; + REG_SET_BIT(ah, AR_PHY_TIMING4, + 1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT); + exit: ar9003_mci_enable_interrupt(ah); return 0; diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index 9a48e3d..8f58523 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h @@ -32,6 +32,7 @@ #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c) #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc) #define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0) +#define AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT 16 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20