From patchwork Wed Apr 15 13:07:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Fietkau X-Patchwork-Id: 6220541 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Original-To: patchwork-linux-wireless@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9C2C4BF4A6 for ; Wed, 15 Apr 2015 13:08:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C1CCA200FF for ; Wed, 15 Apr 2015 13:08:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E40BA20274 for ; Wed, 15 Apr 2015 13:08:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753557AbbDONIF (ORCPT ); Wed, 15 Apr 2015 09:08:05 -0400 Received: from static.88-198-24-112.clients.your-server.de ([88.198.24.112]:60745 "EHLO nbd.name" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753515AbbDONIA (ORCPT ); Wed, 15 Apr 2015 09:08:00 -0400 Received: by nf.lan (Postfix, from userid 501) id 032FBDB7DBA1; Wed, 15 Apr 2015 15:07:53 +0200 (CEST) From: Felix Fietkau To: linux-wireless@vger.kernel.org Cc: kvalo@codeaurora.org, zajec5@gmail.com, hauke@hauke-m.de Subject: [PATCH 1/2] bcma: use absolute base for SoC GPIO pins Date: Wed, 15 Apr 2015 15:07:52 +0200 Message-Id: <1429103273-89272-1-git-send-email-nbd@openwrt.org> X-Mailer: git-send-email 2.2.2 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On some BCM5301x ARM devices, user space still needs to control some system GPIO pins for which no driver exists. This is a lot easier to do with a predictable GPIO base. Signed-off-by: Felix Fietkau --- drivers/bcma/driver_gpio.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/bcma/driver_gpio.c b/drivers/bcma/driver_gpio.c index 74ccb02..9b8d9bf 100644 --- a/drivers/bcma/driver_gpio.c +++ b/drivers/bcma/driver_gpio.c @@ -235,16 +235,17 @@ int bcma_gpio_init(struct bcma_drv_cc *cc) } /* - * On MIPS we register GPIO devices (LEDs, buttons) using absolute GPIO - * pin numbers. We don't have Device Tree there and we can't really use - * relative (per chip) numbers. - * So let's use predictable base for BCM47XX and "random" for all other. + * Register SoC GPIO devices with absolute GPIO pin base. + * On MIPS, we don't have Device Tree and we can't use relative (per chip) + * GPIO numbers. + * On some ARM devices, user space may want to access some system GPIO + * pins directly, which is easier to do with a predictable GPIO base. */ -#if IS_BUILTIN(CONFIG_BCM47XX) - chip->base = bus->num * BCMA_GPIO_MAX_PINS; -#else - chip->base = -1; -#endif + if (IS_BUILTIN(CONFIG_BCM47XX) || + cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) + chip->base = bus->num * BCMA_GPIO_MAX_PINS; + else + chip->base = -1; err = bcma_gpio_irq_domain_init(cc); if (err)