From patchwork Wed May 27 14:17:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalle Valo X-Patchwork-Id: 6490071 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Original-To: patchwork-linux-wireless@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9E2A0C0020 for ; Wed, 27 May 2015 14:18:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8933220425 for ; Wed, 27 May 2015 14:18:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E2C632065D for ; Wed, 27 May 2015 14:18:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752830AbbE0OSK (ORCPT ); Wed, 27 May 2015 10:18:10 -0400 Received: from wolverine02.qualcomm.com ([199.106.114.251]:50810 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752029AbbE0OSH (ORCPT ); Wed, 27 May 2015 10:18:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=qca.qualcomm.com; i=@qca.qualcomm.com; q=dns/txt; s=qcdkim; t=1432736287; x=1464272287; h=from:to:cc:subject:date:message-id:mime-version; bh=2QqH6xBaqcr/PfGdPS//5JQz4RZRYf4MnbXCESEiQ/E=; b=c7zcJQExg5uftwYFH1y/6vUx6VSj/pAJ0Yl2YLvN06jCZAxph1AUpygz 2Cgy2MoRBZOq2rFtAaQBb/TIikhsMfqAxFh4eFmURigz+/tGcq5KWSJn1 1pgjLrnWCzkfJS1di/nDUlD/FUbDKSH+nBwM9qo+qqBCt6FIiWfF81w8x I=; X-IronPort-AV: E=McAfee;i="5700,7163,7813"; a="212856592" Received: from ironmsg01-lv.qualcomm.com ([10.47.202.180]) by wolverine02.qualcomm.com with ESMTP; 27 May 2015 07:18:07 -0700 X-IronPort-AV: E=Sophos;i="5.13,505,1427785200"; d="scan'208";a="33193661" Received: from nasanexm01g.na.qualcomm.com ([10.85.0.33]) by ironmsg01-lv.qualcomm.com with ESMTP/TLS/RC4-SHA; 27 May 2015 07:18:05 -0700 Received: from potku.com (10.80.80.8) by NASANEXM01G.na.qualcomm.com (10.85.0.33) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Wed, 27 May 2015 07:18:00 -0700 From: Kalle Valo To: CC: , Rajkumar Manoharan Subject: [PATCH v4] ath10k: bypass PLL setting on target init for QCA9888 Date: Wed, 27 May 2015 17:17:33 +0300 Message-ID: <1432736253-30040-1-git-send-email-kvalo@qca.qualcomm.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: NASANEXM01B.na.qualcomm.com (10.85.0.82) To NASANEXM01G.na.qualcomm.com (10.85.0.33) Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rajkumar Manoharan Some of of qca988x solutions are having global reset issue during target initialization. Bypassing PLL setting before downloading firmware and letting the SoC run on REF_CLK is fixing the problem. Corresponding firmware change is also needed to set the clock source once the target is initialized. Since 10.2.4 firmware is having this ROM patch, applying skip_clock_init only for 10.2.4 firmware versions. Signed-off-by: Rajkumar Manoharan Signed-off-by: Kalle Valo --- v4: * add ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT * add comment to ath10k_core_start() drivers/net/wireless/ath/ath10k/core.c | 16 ++++++++++++++++ drivers/net/wireless/ath/ath10k/core.h | 3 +++ 2 files changed, 19 insertions(+) diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c index bcccae19325d..e3249630d9d5 100644 --- a/drivers/net/wireless/ath/ath10k/core.c +++ b/drivers/net/wireless/ath/ath10k/core.c @@ -1084,6 +1084,22 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode) if (status) goto err; + /* Some of of qca988x solutions are having global reset issue + * during target initialization. Bypassing PLL setting before + * downloading firmware and letting the SoC run on REF_CLK is + * fixing the problem. Corresponding firmware change is also needed + * to set the clock source once the target is initialized. + */ + if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, + ar->fw_features)) { + status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); + if (status) { + ath10k_err(ar, "could not write to skip_clock_init: %d\n", + status); + goto err; + } + } + status = ath10k_download_fw(ar, mode); if (status) goto err; diff --git a/drivers/net/wireless/ath/ath10k/core.h b/drivers/net/wireless/ath/ath10k/core.h index 70fcdc9c2758..21a8bf166005 100644 --- a/drivers/net/wireless/ath/ath10k/core.h +++ b/drivers/net/wireless/ath/ath10k/core.h @@ -468,6 +468,9 @@ enum ath10k_fw_features { */ ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING, + /* Firmware supports bypassing PLL setting on init. */ + ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9, + /* keep last */ ATH10K_FW_FEATURE_COUNT, };