From patchwork Thu Oct 13 11:27:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prameela Rani Garnepudi X-Patchwork-Id: 9374883 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E40C06075E for ; Thu, 13 Oct 2016 11:44:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D35BB29FFF for ; Thu, 13 Oct 2016 11:44:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C4A882A001; Thu, 13 Oct 2016 11:44:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0FCA629FFF for ; Thu, 13 Oct 2016 11:44:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754891AbcJMLn3 (ORCPT ); Thu, 13 Oct 2016 07:43:29 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:32912 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754519AbcJMLnD (ORCPT ); Thu, 13 Oct 2016 07:43:03 -0400 Received: by mail-pf0-f193.google.com with SMTP id i85so1517381pfa.0 for ; Thu, 13 Oct 2016 04:42:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=j8gaoTliappat5dM/j0XARqiqHU1h9MF1Y07Q5tepmQ=; b=J7NfEOul5liWnc479wllphdf2P5AUVEJkJ+btj1a8YZWOAESiO5LDG8MfAFfA5S7Ii S+1XS1rcwTZyQkHJgdep0QfPa+BvL9W06NKZYfT/2qg6zRJv1r154B3r/CMQEyJBvSwf dSxbAnORqD+XrrKFv/TfQRp3s9Qhv5AepMQ9WcA4p8lj7FIqJ5/lgOD9LNu6O5bmy6LF ootGkZUsXGUdr79ngPzRU+JugOluh5PbLh85dB0q0izmWDJJJsJKGm5JbBcbs9rCWwTK YxULXgHiRyy/Hzk00Xnm3z13q/A4qXs2bpxSMHv5eRCTzGNwqT/Iet1Vf7meJp4nHCjJ GgzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=j8gaoTliappat5dM/j0XARqiqHU1h9MF1Y07Q5tepmQ=; b=m8DHOYElLStL6n1p6WHLsHKVsYvc+Wd+iakv92cirPCvVUKLj+wpC44ok58DlJVdHh 3k40CkPyTvA/VloqdzJa7TcYn9gektGkPYEoNCDsrGfgJi3d7VUUgheUu20mR1n3CYjO cfAmxJlD/p9kx+VfWj5x4LwUASIWYXfVtiSafQm+0usk7y9WoqXln7ka+yw5aj17JbmR hKHwXyHhjHPsJift1ing2o0vUs8cCITgVJ2eVevX160IZoUMhDh2hhYxHjU4gcaXAGRR Ct7gSBOVsl/+r4XkvdHAzhWlhITDCbGeNyzTNnxDFU2h9Q9HImcQ4NbnIoJBZYz/DAjI GaCA== X-Gm-Message-State: AA6/9RkVtNGaRZPT+FQ5LTrAHjFu0LcJ6OWk/5Q1smG1vb1icud+QKRccnvpg1erfk8oSA== X-Received: by 10.98.198.25 with SMTP id m25mr9228833pfg.144.1476358214194; Thu, 13 Oct 2016 04:30:14 -0700 (PDT) Received: from lapt225.localdomain ([203.196.161.90]) by smtp.gmail.com with ESMTPSA id aa6sm19011976pad.46.2016.10.13.04.30.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Oct 2016 04:30:13 -0700 (PDT) From: Prameela Rani Garnepudi To: linux-wireless@vger.kernel.org Cc: kvalo@codeaurora.org, johannes.berg@intel.com, hofrat@osadl.org, xypron.glpk@gmx.de, prameela.garnepudi@redpinesignals.com, Prameela Rani Garnepudi Subject: [PATCH 3/3] rsi: Updated boot parameters Date: Thu, 13 Oct 2016 16:57:05 +0530 Message-Id: <1476358025-15576-1-git-send-email-prameela.j04cs@gmail.com> X-Mailer: git-send-email 2.4.11 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP * Switch clock info is divided in to different clock information fields for readability and synchronization with firmware code. * Other parameters are added for future use and to make the frame size in sync with latest firmware. Otherwise firmware will discard the frame considering corrupted frame. Signed-off-by: Prameela Rani Garnepudi --- drivers/net/wireless/rsi/rsi_91x_mgmt.c | 62 ++++++++++++++++++++++++++---- drivers/net/wireless/rsi/rsi_boot_params.h | 45 +++++++++++++++++++++- 2 files changed, 97 insertions(+), 10 deletions(-) diff --git a/drivers/net/wireless/rsi/rsi_91x_mgmt.c b/drivers/net/wireless/rsi/rsi_91x_mgmt.c index 30b9d44..10796c2 100644 --- a/drivers/net/wireless/rsi/rsi_91x_mgmt.c +++ b/drivers/net/wireless/rsi/rsi_91x_mgmt.c @@ -18,6 +18,7 @@ #include "rsi_mgmt.h" #include "rsi_common.h" +/* Bootup Parameters for 20MHz */ static struct bootup_params boot_params_20 = { .magic_number = cpu_to_le16(0x5aa5), .crystal_good_time = 0x0, @@ -28,6 +29,7 @@ static struct bootup_params boot_params_20 = { .rtls_timestamp_en = 0x0, .host_spi_intr_cfg = 0x0, .device_clk_info = {{ + /* WLAN params */ .pll_config_g = { .tapll_info_g = { .pll_reg_1 = cpu_to_le16((TA_PLL_N_VAL_20 << 8)| @@ -45,12 +47,18 @@ static struct bootup_params boot_params_20 = { } }, .switch_clk_g = { - .switch_clk_info = cpu_to_le16(BIT(3)), + .switch_umac_clk = 0x0, + .switch_qspi_clk = 0x0, + .switch_slp_clk_2_32 = 0x0, + .switch_bbp_lmac_clk_reg = 0x1, + .switch_mem_ctrl_cfg = 0x0, + .reserved = 0x0, .bbp_lmac_clk_reg_val = cpu_to_le16(0x121), .umac_clock_reg_config = 0x0, .qspi_uart_clock_reg_config = 0x0 } }, + /* Bluetooth params */ { .pll_config_g = { .tapll_info_g = { @@ -69,12 +77,18 @@ static struct bootup_params boot_params_20 = { } }, .switch_clk_g = { - .switch_clk_info = 0x0, + .switch_umac_clk = 0x0, + .switch_qspi_clk = 0x0, + .switch_slp_clk_2_32 = 0x0, + .switch_bbp_lmac_clk_reg = 0x0, + .switch_mem_ctrl_cfg = 0x0, + .reserved = 0x0, .bbp_lmac_clk_reg_val = 0x0, .umac_clock_reg_config = 0x0, .qspi_uart_clock_reg_config = 0x0 } }, + /* Zigbee params */ { .pll_config_g = { .tapll_info_g = { @@ -93,12 +107,18 @@ static struct bootup_params boot_params_20 = { } }, .switch_clk_g = { - .switch_clk_info = 0x0, + .switch_umac_clk = 0x0, + .switch_qspi_clk = 0x0, + .switch_slp_clk_2_32 = 0x0, + .switch_bbp_lmac_clk_reg = 0x0, + .switch_mem_ctrl_cfg = 0x0, + .reserved = 0x0, .bbp_lmac_clk_reg_val = 0x0, .umac_clock_reg_config = 0x0, .qspi_uart_clock_reg_config = 0x0 } } }, + /* ULP Params */ .buckboost_wakeup_cnt = 0x0, .pmu_wakeup_wait = 0x0, .shutdown_wait_time = 0x0, @@ -106,9 +126,13 @@ static struct bootup_params boot_params_20 = { .wdt_prog_value = 0x0, .wdt_soc_rst_delay = 0x0, .dcdc_operation_mode = 0x0, - .soc_reset_wait_cnt = 0x0 + .soc_reset_wait_cnt = 0x0, + .waiting_time_at_fresh_sleep = 0x0, + .max_threshold_to_avoid_sleep = 0x0, + .beacon_resedue_alg_en = 0, }; +/* Bootup parameters for 40MHz */ static struct bootup_params boot_params_40 = { .magic_number = cpu_to_le16(0x5aa5), .crystal_good_time = 0x0, @@ -119,6 +143,7 @@ static struct bootup_params boot_params_40 = { .rtls_timestamp_en = 0x0, .host_spi_intr_cfg = 0x0, .device_clk_info = {{ + /* WLAN params */ .pll_config_g = { .tapll_info_g = { .pll_reg_1 = cpu_to_le16((TA_PLL_N_VAL_40 << 8)| @@ -136,12 +161,18 @@ static struct bootup_params boot_params_40 = { } }, .switch_clk_g = { - .switch_clk_info = cpu_to_le16(0x09), + .switch_umac_clk = 0x1, + .switch_qspi_clk = 0x0, + .switch_slp_clk_2_32 = 0x0, + .switch_bbp_lmac_clk_reg = 0x1, + .switch_mem_ctrl_cfg = 0x0, + .reserved = 0x0, .bbp_lmac_clk_reg_val = cpu_to_le16(0x1121), .umac_clock_reg_config = cpu_to_le16(0x48), .qspi_uart_clock_reg_config = 0x0 } }, + /* Bluetooth Params */ { .pll_config_g = { .tapll_info_g = { @@ -160,12 +191,18 @@ static struct bootup_params boot_params_40 = { } }, .switch_clk_g = { - .switch_clk_info = 0x0, + .switch_umac_clk = 0x0, + .switch_qspi_clk = 0x0, + .switch_slp_clk_2_32 = 0x0, + .switch_bbp_lmac_clk_reg = 0x0, + .switch_mem_ctrl_cfg = 0x0, + .reserved = 0x0, .bbp_lmac_clk_reg_val = 0x0, .umac_clock_reg_config = 0x0, .qspi_uart_clock_reg_config = 0x0 } }, + /* Zigbee Params */ { .pll_config_g = { .tapll_info_g = { @@ -184,12 +221,18 @@ static struct bootup_params boot_params_40 = { } }, .switch_clk_g = { - .switch_clk_info = 0x0, + .switch_umac_clk = 0x0, + .switch_qspi_clk = 0x0, + .switch_slp_clk_2_32 = 0x0, + .switch_bbp_lmac_clk_reg = 0x0, + .switch_mem_ctrl_cfg = 0x0, + .reserved = 0x0, .bbp_lmac_clk_reg_val = 0x0, .umac_clock_reg_config = 0x0, .qspi_uart_clock_reg_config = 0x0 } } }, + /* ULP Params */ .buckboost_wakeup_cnt = 0x0, .pmu_wakeup_wait = 0x0, .shutdown_wait_time = 0x0, @@ -197,7 +240,10 @@ static struct bootup_params boot_params_40 = { .wdt_prog_value = 0x0, .wdt_soc_rst_delay = 0x0, .dcdc_operation_mode = 0x0, - .soc_reset_wait_cnt = 0x0 + .soc_reset_wait_cnt = 0x0, + .waiting_time_at_fresh_sleep = 0x0, + .max_threshold_to_avoid_sleep = 0x0, + .beacon_resedue_alg_en = 0, }; static u16 mcs[] = {13, 26, 39, 52, 78, 104, 117, 130}; diff --git a/drivers/net/wireless/rsi/rsi_boot_params.h b/drivers/net/wireless/rsi/rsi_boot_params.h index 5e2721f..c1be104 100644 --- a/drivers/net/wireless/rsi/rsi_boot_params.h +++ b/drivers/net/wireless/rsi/rsi_boot_params.h @@ -81,7 +81,13 @@ struct pll_config { /* structure to store configs related to UMAC clk programming */ struct switch_clk { - __le16 switch_clk_info; + __le16 switch_umac_clk : 1; /* If set rest is valid */ + __le16 switch_qspi_clk : 1; /* If set qspi clk will be changed */ + __le16 switch_slp_clk_2_32 : 1; + __le16 switch_bbp_lmac_clk_reg : 1; + __le16 switch_mem_ctrl_cfg : 1; + __le16 reserved : 11; + /* If switch_bbp_lmac_clk_reg is set then this value will be programmed * into reg */ @@ -99,11 +105,43 @@ struct device_clk_info { struct bootup_params { __le16 magic_number; +#define LOADED_TOKEN 0x5AA5 /* Bootup params are installed by host + * or OTP/FLASH (Bootloader) + */ +#define ROM_TOKEN 0x55AA /* Bootup params are taken from ROM + * itself in MCU mode. + */ __le16 crystal_good_time; __le32 valid; +#define CRYSTAL_GOOD_TIME BIT(0) +#define BOOTUP_MODE_INFO BIT(1) +#define DIGITAL_LOOP_BACK_PARAMS BIT(2) +#define RTLS_TIMESTAMP_EN BIT(3) +#define HOST_SPI_INTR_CFG BIT(4) +#define WIFI_TAPLL_CONFIGS BIT(5) +#define WIFI_PLL960_CONFIGS BIT(6) +#define WIFI_AFEPLL_CONFIGS BIT(7) +#define WIFI_SWITCH_CLK_CONFIGS BIT(8) +#define BT_TAPLL_CONFIGS BIT(9) +#define BT_PLL960_CONFIGS BIT(10) +#define BT_AFEPLL_CONFIGS BIT(11) +#define BT_SWITCH_CLK_CONFIGS BIT(12) +#define ZB_TAPLL_CONFIGS BIT(13) +#define ZB_PLL960_CONFIGS BIT(14) +#define ZB_AFEPLL_CONFIGS BIT(15) +#define ZB_SWITCH_CLK_CONFIGS BIT(16) +#define BUCKBOOST_WAIT_INFO BIT(17) +#define PMU_WAKEUP_SHUTDOWN_W BIT(18) +#define WDT_PROG_VALUES BIT(19) +#define WDT_RESET_DELAY_VALUE BIT(20) +#define DCDC_OPERATION_MODE_VALID BIT(21) +#define PMU_SLP_CLKOUT_SEL BIT(22) +#define SOC_RESET_WAIT_CNT BIT(23) __le32 reserved_for_valids; __le16 bootup_mode_info; - /* configuration used for digital loop back */ +#define BT_COEXIST BIT(0) +#define BOOTUP_MODE (BIT(2) | BIT(1)) +#define CUR_DEV_MODE (bootup_params.bootup_mode_info >> 1) __le16 digital_loop_back_params; __le16 rtls_timestamp_en; __le16 host_spi_intr_cfg; @@ -122,5 +160,8 @@ struct bootup_params { /* dcdc modes configs */ __le32 dcdc_operation_mode; __le32 soc_reset_wait_cnt; + __le32 waiting_time_at_fresh_sleep; + __le32 max_threshold_to_avoid_sleep; + u8 beacon_resedue_alg_en; } __packed; #endif