From patchwork Wed Apr 3 21:21:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenghua Yu X-Patchwork-Id: 10884467 X-Patchwork-Delegate: johannes@sipsolutions.net Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2AB11575 for ; Wed, 3 Apr 2019 21:31:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC81E284C7 for ; Wed, 3 Apr 2019 21:31:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CFFE5285C7; Wed, 3 Apr 2019 21:31:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 77C9E284C7 for ; Wed, 3 Apr 2019 21:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727951AbfDCVbF (ORCPT ); Wed, 3 Apr 2019 17:31:05 -0400 Received: from mga05.intel.com ([192.55.52.43]:37312 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726772AbfDCVaV (ORCPT ); Wed, 3 Apr 2019 17:30:21 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Apr 2019 14:30:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,306,1549958400"; d="scan'208";a="334754243" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga005.fm.intel.com with ESMTP; 03 Apr 2019 14:30:11 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Dave Hansen" , "Paolo Bonzini" , "Ashok Raj" , "Peter Zijlstra" , "Kalle Valo" , "Xiaoyao Li " , "Michael Chan" , "Ravi V Shankar" Cc: "linux-kernel" , "x86" , linux-wireless@vger.kernel.org, netdev@vger.kernel.org, kvm@vger.kernel.org, Fenghua Yu Subject: [PATCH v6 08/20] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Date: Wed, 3 Apr 2019 14:21:54 -0700 Message-Id: <1554326526-172295-9-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1554326526-172295-1-git-send-email-fenghua.yu@intel.com> References: <1554326526-172295-1-git-send-email-fenghua.yu@intel.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Icelake mobile processor can detect split lock operations although the processor doesn't have MSR_IA32_CORE_CAPABILITY and split lock detection bit in the MSR. Set split lock detection feature bit X86_FEATURE_SPLIT_LOCK_DETECT on the processor based on its family/model/stepping. A few other processors may also have the feature but don't have MSR_IA32_CORE_CAPABILITY. The feature will be enumerated on those processors once their family/model/stepping information is released. Signed-off-by: Fenghua Yu --- arch/x86/kernel/cpu/intel.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index ad3f72d106fc..7f6943af35dc 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -1038,8 +1038,18 @@ void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) { u64 ia32_core_cap = 0; - if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITY)) + if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITY)) { + /* + * The following processors have split lock detection feature. + * But since they don't have MSR_IA32_CORE_CAPABILITY, the + * feature cannot be enumerated by the MSR. So enumerate the + * feature by family/model/stepping. + */ + if (c->x86 == 6 && c->x86_model == INTEL_FAM6_ICELAKE_MOBILE) + set_split_lock_detect(); + return; + } /* * If MSR_IA32_CORE_CAPABILITY exists, enumerate features that are