[RFC,v1,160/256] cl8k: add reg/reg_mac_hw_mu.h

Commit Message

Viktor Barna June 17, 2021, 4 p.m. UTC

From: Viktor Barna <[e-mail]>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <[e-mail]>
---
 .../wireless/celeno/cl8k/reg/reg_mac_hw_mu.h  | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw_mu.h

--
2.30.0

Patch

diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw_mu.h b/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw_mu.h
new file mode 100644
index 000000000000..45368cfc36d6
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw_mu.h
@@ -0,0 +1,33 @@ 
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_MAC_HW_MU_H
+#define CL_REG_MAC_HW_MU_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "hw.h"
+
+#define MU_ADDR_OFFSET(i) ((i) << 16)
+
+/*
+ * @brief MAC_CNTRL_2 register definition
+ * Contains various settings for controlling the operation of the core. register description
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   00    SOFT_RESET                0
+ * </pre>
+ */
+#define MAC_HW_MU_MAC_CNTRL_2_ADDR        (REG_MAC_HW_BASE_ADDR + 0x00008050)
+#define MAC_HW_MU_MAC_CNTRL_2_OFFSET      0x00008050
+#define MAC_HW_MU_MAC_CNTRL_2_INDEX       0x00002014
+#define MAC_HW_MU_MAC_CNTRL_2_RESET       0x00000000
+
+static inline void  mac_hw_mu_mac_cntrl_2_set(struct cl_hw *cl_hw, u32 value, u8 mu_idx)
+{
+       ASSERT_ERR(mu_idx < cl_hw->max_mu_cnt);
+       cl_reg_write(cl_hw, (MAC_HW_MU_MAC_CNTRL_2_ADDR + MU_ADDR_OFFSET(mu_idx)), value);
+}
+
+#endif /* CL_REG_MAC_HW_MU_H */