From patchwork Sat Jan 31 00:14:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Oh X-Patchwork-Id: 5753541 Return-Path: X-Original-To: patchwork-linux-wireless@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 529869F302 for ; Sat, 31 Jan 2015 00:14:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 84D77202A1 for ; Sat, 31 Jan 2015 00:14:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 49D7A2028D for ; Sat, 31 Jan 2015 00:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759549AbbAaAOp (ORCPT ); Fri, 30 Jan 2015 19:14:45 -0500 Received: from wolverine02.qualcomm.com ([199.106.114.251]:9578 "EHLO wolverine02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752684AbbAaAOo (ORCPT ); Fri, 30 Jan 2015 19:14:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=qca.qualcomm.com; i=@qca.qualcomm.com; q=dns/txt; s=qcdkim; t=1422663284; x=1454199284; h=from:to:cc:subject:date:message-id:mime-version; bh=gW6mjq1fgg2wfpSGL1J3HzvfnOf6yiiGEAQfZ8suyiE=; b=ESXt9oztIK2q6q+pTcqqDN+BOJCfiOJZFAhIHON/n2fckWM6OcOOqgJU tf9xlyFPj2CWWofZuGjJAfLYSm5sSx66s0qf/ms/hz5rBjV5HjukK0rKV lf9d834mTGnRhbcsnaZtoaWEZxldb6j32iZcGu0VrAG5t+6RzLnBFbCpq o=; X-IronPort-AV: E=McAfee;i="5600,1067,7697"; a="193019003" Received: from ironmsg02-lv.qualcomm.com ([10.47.202.183]) by wolverine02.qualcomm.com with ESMTP; 30 Jan 2015 16:14:44 -0800 X-IronPort-AV: E=Sophos;i="5.09,494,1418112000"; d="scan'208";a="31630450" Received: from nasanexm01b.na.qualcomm.com ([10.85.0.82]) by ironmsg02-lv.qualcomm.com with ESMTP/TLS/RC4-SHA; 30 Jan 2015 16:14:43 -0800 Received: from poh-linux2.qualcomm.com (10.80.80.8) by NASANEXM01B.na.qualcomm.com (10.85.0.82) with Microsoft SMTP Server (TLS) id 15.0.995.29; Fri, 30 Jan 2015 16:14:42 -0800 From: Peter Oh To: CC: Subject: [PATCH v2] ath10k: Replace ioread with mb to drain write buffer Date: Fri, 30 Jan 2015 16:14:30 -0800 Message-ID: <7a87e5df81499e4d26a4f8bedf76ed3250a6f7bb.1422663244.git.poh@qca.qualcomm.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: NASANEXM01G.na.qualcomm.com (10.85.0.33) To NASANEXM01B.na.qualcomm.com (10.85.0.82) Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Using ioread() to perform draining write buffer is excessive. Use compact API, mb(), that intended to be used for the case. It reduces total 14 CPU clocks per interrupt. Signed-off-by: Peter Oh --- drivers/net/wireless/ath/ath10k/pci.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c index e6972b0..f1e6980 100644 --- a/drivers/net/wireless/ath/ath10k/pci.c +++ b/drivers/net/wireless/ath/ath10k/pci.c @@ -353,10 +353,8 @@ static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); - /* IMPORTANT: this extra read transaction is required to - * flush the posted write buffer. */ - (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + - PCIE_INTR_ENABLE_ADDRESS); + /* drain write buffer */ + mb(); } static void ath10k_pci_enable_legacy_irq(struct ath10k *ar) @@ -365,10 +363,8 @@ static void ath10k_pci_enable_legacy_irq(struct ath10k *ar) PCIE_INTR_ENABLE_ADDRESS, PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); - /* IMPORTANT: this extra read transaction is required to - * flush the posted write buffer. */ - (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + - PCIE_INTR_ENABLE_ADDRESS); + /* drain write buffer */ + mb(); } static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)