From patchwork Mon Oct 5 15:57:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryder Lee X-Patchwork-Id: 11816923 X-Patchwork-Delegate: nbd@nbd.name Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99441139A for ; Mon, 5 Oct 2020 15:58:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A0D32068E for ; Mon, 5 Oct 2020 15:58:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IYI7sKCY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727171AbgJEP6A (ORCPT ); Mon, 5 Oct 2020 11:58:00 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:49528 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726057AbgJEP6A (ORCPT ); Mon, 5 Oct 2020 11:58:00 -0400 X-UUID: 86bfad94d67d4384ab6d1d5b99219fdf-20201005 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=Ki3wTt7d1tvRrJ2MPiGpeliJV3ST6qE/ddjlBK6ldMA=; b=IYI7sKCYNmCiWPaOLv063Hrbd6uYxQ4JXI79b/3l8kalxPlLGncBVqEcEf54FZ4JR2ko1YDMNemi3ThtcH6nbo8W9c5cE/Nhdk6C3foOevISJ20HfehmsNgjdYrt5VQBvTg4RgfqAr1eoNTBcbebm+G7Hc8jBJFyqRWFYtn55nc=; X-UUID: 86bfad94d67d4384ab6d1d5b99219fdf-20201005 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2106959968; Mon, 05 Oct 2020 23:57:57 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Oct 2020 23:57:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 5 Oct 2020 23:57:54 +0800 From: Ryder Lee To: Felix Fietkau , Lorenzo Bianconi CC: Shayne Chen , Evelyn Tsai , , , Ryder Lee Subject: [PATCH 1/2] mt76: mt7915: update ppe threshold Date: Mon, 5 Oct 2020 23:57:52 +0800 Message-ID: X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: AD7E908D8DDEDB847D2F270C7FD6F6B51A40574D610DE60E869CDEE11431880B2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Update ppe_thresh capability to sync SDK setting. Signed-off-by: Shayne Chen Signed-off-by: Ryder Lee --- .../net/wireless/mediatek/mt76/mt7915/init.c | 43 +++++++------------ 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c index 5884c0ce45e5..f340cc5f78da 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c @@ -357,35 +357,24 @@ mt7915_set_stream_he_txbf_caps(struct ieee80211_sta_he_cap *he_cap, } static void -mt7915_gen_ppe_thresh(u8 *he_ppet) +mt7915_gen_ppe_thresh(u8 *he_ppet, int nss) { - int ru, nss, max_nss = 1, max_ru = 3; - u8 bit = 7, ru_bit_mask = 0x7; + u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */ u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71}; - he_ppet[0] = max_nss & IEEE80211_PPE_THRES_NSS_MASK; - he_ppet[0] |= (ru_bit_mask << - IEEE80211_PPE_THRES_RU_INDEX_BITMASK_POS) & - IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK; - - for (nss = 0; nss <= max_nss; nss++) { - for (ru = 0; ru < max_ru; ru++) { - u8 val; - int i; - - if (!(ru_bit_mask & BIT(ru))) - continue; - - val = (ppet16_ppet8_ru3_ru0[nss] >> (ru * 6)) & - 0x3f; - val = ((val >> 3) & 0x7) | ((val & 0x7) << 3); - for (i = 5; i >= 0; i--) { - he_ppet[bit / 8] |= - ((val >> i) & 0x1) << ((bit % 8)); - bit++; - } - } - } + he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) | + FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, + ru_bit_mask); + + ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE * + nss * hweight8(ru_bit_mask) * 2; + ppet_size = DIV_ROUND_UP(ppet_bits, 8); + + for (i = 0; i < ppet_size - 1; i++) + he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3]; + + he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] & + (0xff >> (8 - (ppet_bits - 1) % 8)); } static int @@ -516,7 +505,7 @@ mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); if (he_cap_elem->phy_cap_info[6] & IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { - mt7915_gen_ppe_thresh(he_cap->ppe_thres); + mt7915_gen_ppe_thresh(he_cap->ppe_thres, nss); } else { he_cap_elem->phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US;