From patchwork Tue Mar 31 06:51:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryder Lee X-Patchwork-Id: 11466773 X-Patchwork-Delegate: nbd@nbd.name Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1057D92A for ; Tue, 31 Mar 2020 06:51:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D97DD20757 for ; Tue, 31 Mar 2020 06:51:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="kKAvCiQZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729949AbgCaGvv (ORCPT ); Tue, 31 Mar 2020 02:51:51 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:59223 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726299AbgCaGvv (ORCPT ); Tue, 31 Mar 2020 02:51:51 -0400 X-UUID: 4b49966a83ff461db690b092e6bfd3be-20200331 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dWeUYI7xrUUPpwG9uIR3lS1sfk04c5uMrHZowKdcRA8=; b=kKAvCiQZlWcsvD4NLcuYMZM3Bmt7JKbTHxendko8EMmDGkfrhyT3d/J/qQpNmfP0KWtANPK50DnwjHHvIcj9ZO+3k7P1ZMLwYnnMCJZ8kOyozbF6t4d3zWqeDRpVfOeIzi/G9NhUx59yKaxnHDynAw1b4gaAOgz3B+bEUyOs5L8=; X-UUID: 4b49966a83ff461db690b092e6bfd3be-20200331 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 94718106; Tue, 31 Mar 2020 14:51:41 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 31 Mar 2020 14:51:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 31 Mar 2020 14:51:39 +0800 From: Ryder Lee To: Felix Fietkau , Lorenzo Bianconi CC: Shayne Chen , Sean Wang , , , Ryder Lee Subject: [PATCH 3/4] mt76: mt7615: cleanup mib related defines and structs Date: Tue, 31 Mar 2020 14:51:37 +0800 Message-ID: X-Mailer: git-send-email 2.18.0 In-Reply-To: <1fc90ec2a64d062ac7264aaa3dd158f2282ad7b8.1585636614.git.ryder.lee@mediatek.com> References: <1fc90ec2a64d062ac7264aaa3dd158f2282ad7b8.1585636614.git.ryder.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Simplify mib macros and use proper type for related counters. Signed-off-by: Ryder Lee --- .../net/wireless/mediatek/mt76/mt7615/mac.c | 16 ++++++------- .../wireless/mediatek/mt76/mt7615/mt7615.h | 8 +++---- .../net/wireless/mediatek/mt76/mt7615/regs.h | 23 ++++++++----------- 3 files changed, 22 insertions(+), 25 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/mac.c b/drivers/net/wireless/mediatek/mt76/mt7615/mac.c index 8572973cc4c8..f30dc015e88e 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7615/mac.c @@ -1535,8 +1535,8 @@ void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable) mt76_set(dev, MT_WF_PHY_MIN_PRI_PWR(1), MT_WF_PHY_PD_BLK(1)); if (is_mt7622(&dev->mt76)) { - mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7 << 8); - mt76_set(dev, MT_MIB_M0_MISC_CR, 0x7); + mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); + mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); } } else { mt76_clear(dev, MT_WF_PHY_MIN_PRI_PWR(0), @@ -1762,18 +1762,18 @@ mt7615_mac_update_mib_stats(struct mt7615_phy *phy) aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; for (i = 0; i < 4; i++) { - u32 data, val, val2; + u32 val, val2; val = mt76_get_field(dev, MT_MIB_MB_SDR1(ext_phy, i), MT_MIB_ACK_FAIL_COUNT_MASK); if (val > mib->ack_fail_cnt) mib->ack_fail_cnt = val; - val2 = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); - data = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val2); - if (data > mib->rts_retries_cnt) { - mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val2); - mib->rts_retries_cnt = data; + val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); + val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); + if (val2 > mib->rts_retries_cnt) { + mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); + mib->rts_retries_cnt = val2; } val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h b/drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h index 676ca622c35a..000070769217 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h +++ b/drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h @@ -113,10 +113,10 @@ struct mt7615_vif { }; struct mib_stats { - u32 ack_fail_cnt; - u32 fcs_err_cnt; - u32 rts_cnt; - u32 rts_retries_cnt; + u16 ack_fail_cnt; + u16 fcs_err_cnt; + u16 rts_cnt; + u16 rts_retries_cnt; }; struct mt7615_phy { diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/regs.h b/drivers/net/wireless/mediatek/mt76/mt7615/regs.h index d91041613df8..58aaa57fb451 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/regs.h +++ b/drivers/net/wireless/mediatek/mt76/mt7615/regs.h @@ -379,35 +379,32 @@ enum mt7615_reg_base { #define MT_LPON_UTTR1 MT_LPON(0x01c) #define MT_WF_MIB_BASE (dev->reg_map[MT_MIB_BASE]) -#define MT_WF_MIB(ofs) (MT_WF_MIB_BASE + (ofs)) +#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE + (ofs) + (_band) * 0x200) -#define MT_MIB_M0_MISC_CR MT_WF_MIB(0x00c) +#define MT_MIB_M0_MISC_CR(_band) MT_WF_MIB(_band, 0x00c) -#define MT_MIB_SDR3(n) MT_WF_MIB(0x014 + ((n) << 9)) +#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014) #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) -#define MT_MIB_SDR9(n) MT_WF_MIB(0x02c + ((n) << 9)) +#define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c) #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0) -#define MT_MIB_SDR16(n) MT_WF_MIB(0x048 + ((n) << 9)) +#define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048) #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0) -#define MT_MIB_SDR36(n) MT_WF_MIB(0x098 + ((n) << 9)) +#define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098) #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0) -#define MT_MIB_SDR37(n) MT_WF_MIB(0x09c + ((n) << 9)) +#define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c) #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0) -#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(0x100 + ((_band) << 9) + \ - ((n) << 4)) +#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4)) #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) -#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(0x104 + ((_band) << 9) + \ - ((n) << 4)) +#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4)) #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) -#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(0xa8 + ((_band) << 9) + \ - ((n) << 2)) +#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa8 + ((n) << 2)) #define MT_DMA_SHDL(ofs) (dev->reg_map[MT_DMA_SHDL_BASE] + (ofs))