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[net-next,00/13] Add NXP SJA1110 support to the sja1105 DSA driver

Message ID 20210524232214.1378937-1-olteanv@gmail.com (mailing list archive)
Headers show
Series Add NXP SJA1110 support to the sja1105 DSA driver | expand

Message

Vladimir Oltean May 24, 2021, 11:22 p.m. UTC
From: Vladimir Oltean <vladimir.oltean@nxp.com>

The NXP SJA1110 is an automotive Ethernet switch with an embedded Arm
Cortex-M7 microcontroller. The switch has 11 ports (10 external + one
for the DSA-style connection to the microcontroller).
The microcontroller can be disabled and the switch can be controlled
over SPI, a la SJA1105 - this is how this driver handles things.

There are some integrated NXP PHYs (100base-T1 and 100base-TX). Their
initialization is handled by their own PHY drivers, the switch is only
concerned with enabling register accesses to them, by registering two
MDIO buses.

PHY interrupts might be possible, however I believe that the board I am
working on does not have them wired, which makes things a bit more
difficult to test.

Cc: Russell King <linux@armlinux.org.uk>

Vladimir Oltean (13):
  net: dsa: sja1105: be compatible with "ethernet-ports" OF node name
  net: dsa: sja1105: allow SGMII PCS configuration to be per port
  net: dsa: sja1105: the 0x1F0000 SGMII "base address" is actually
    MDIO_MMD_VEND2
  net: dsa: sja1105: cache the phy-mode port property
  net: dsa: sja1105: add a PHY interface type compatibility matrix
  net: dsa: sja1105: add a translation table for port speeds
  net: dsa: sja1105: always keep RGMII ports in the MAC role
  net: dsa: sja1105: some table entries are always present when read
    dynamically
  dt-bindings: net: dsa: sja1105: add compatible strings for SJA1110
  net: dsa: sja1105: add support for the SJA1110 switch family
  net: dsa: sja1105: register the MDIO buses for 100base-T1 and
    100base-TX
  net: dsa: sja1105: expose the SGMII PCS as an mdio_device
  net: dsa: sja1105: add support for the SJA1110 SGMII/2500base-x PCS

 .../devicetree/bindings/net/dsa/sja1105.txt   |   4 +
 drivers/net/dsa/sja1105/Makefile              |   1 +
 drivers/net/dsa/sja1105/sja1105.h             |  88 ++-
 drivers/net/dsa/sja1105/sja1105_clocking.c    | 120 +++-
 .../net/dsa/sja1105/sja1105_dynamic_config.c  | 336 ++++++++++-
 .../net/dsa/sja1105/sja1105_dynamic_config.h  |   1 +
 drivers/net/dsa/sja1105/sja1105_main.c        | 518 +++++++++++++----
 drivers/net/dsa/sja1105/sja1105_mdio.c        | 530 ++++++++++++++++++
 drivers/net/dsa/sja1105/sja1105_sgmii.h       |  63 ++-
 drivers/net/dsa/sja1105/sja1105_spi.c         | 368 +++++++++++-
 .../net/dsa/sja1105/sja1105_static_config.c   | 483 ++++++++++++++++
 .../net/dsa/sja1105/sja1105_static_config.h   |  98 +++-
 12 files changed, 2442 insertions(+), 168 deletions(-)
 create mode 100644 drivers/net/dsa/sja1105/sja1105_mdio.c

Comments

Andrew Lunn May 25, 2021, 2:03 a.m. UTC | #1
> There are some integrated NXP PHYs (100base-T1 and 100base-TX). Their
> initialization is handled by their own PHY drivers, the switch is only
> concerned with enabling register accesses to them, by registering two
> MDIO buses.
> 
> PHY interrupts might be possible, however I believe that the board I am
> working on does not have them wired, which makes things a bit more
> difficult to test.

In general, internal PHYs have an internal interrupt controller, often
in the switch register space. There then might be one interrupt from
the switch to the host. It could be this one interrupt is missing on
your board. But this is also quite common with mv88e6xxx boards. So i
added code to poll the interrupt bit, i think 10 times per
second. Polling one bit 10 times a second is more efficient than
having phylib poll each PHY every second when it needs to read a
number of registers. And the latency is better.

       Andrew
Vladimir Oltean May 26, 2021, 12:51 p.m. UTC | #2
On Tue, May 25, 2021 at 04:03:47AM +0200, Andrew Lunn wrote:
> > There are some integrated NXP PHYs (100base-T1 and 100base-TX). Their
> > initialization is handled by their own PHY drivers, the switch is only
> > concerned with enabling register accesses to them, by registering two
> > MDIO buses.
> > 
> > PHY interrupts might be possible, however I believe that the board I am
> > working on does not have them wired, which makes things a bit more
> > difficult to test.
> 
> In general, internal PHYs have an internal interrupt controller, often
> in the switch register space. There then might be one interrupt from
> the switch to the host. It could be this one interrupt is missing on
> your board. But this is also quite common with mv88e6xxx boards. So i
> added code to poll the interrupt bit, i think 10 times per
> second. Polling one bit 10 times a second is more efficient than
> having phylib poll each PHY every second when it needs to read a
> number of registers. And the latency is better.

That is a good suggestion and probably what I'll end up doing, but not
in this patch series since it is already on the heavy side, and getting
access to the interrupt status registers isn't easy-peasy.