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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id z8sm9462678ejd.94.2021.10.06.15.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Oct 2021 15:36:28 -0700 (PDT) From: Ansuel Smith To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , Ansuel Smith , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next PATCH 00/13] Multiple improvement for qca8337 switch Date: Thu, 7 Oct 2021 00:35:50 +0200 Message-Id: <20211006223603.18858-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org This series is the final step of a long process of porting 80+ devices to use the new qca8k driver instead of the hacky qca one based on never merged swconfig platform. Some background to justify all these additions. QCA used a special binding to declare raw initval to set the swich. I made a script to convert all these magic values and convert 80+ dts and scan all the needed "unsupported regs". We find a baseline where we manage to find the common and used regs so in theory hopefully we don't have to add anymore things. We discovered lots of things with this, especially about how differently qca8327 works compared to qca8337. In short, we found that qca8327 have some problem with suspend/resume for their internal phy. It instead sets some dedicated regs that suspend the phy without setting the standard bit. First 4 patch are to fix this. There is also a patch about preferring master. This is directly from the original driver and it seems to be needed to prevent some problem with the pause frame. Every ipq806x target sets the mac power sel and this specific reg regulates the output voltage of the regulator. Without this some instability can occur. Some configuration (for some reason) swap mac6 with mac0. We add support for this. Also, we discovered that some device doesn't work at all with pll enabled for sgmii line. In the original code this was based on the switch revision. In later revision the pll regs were decided based on the switch type (disabled for qca8327 and enabled for qca8337) but still some device had that disabled in the initval regs. Considering we found at least one qca8337 device that required pll disabled to work (no traffic problem) we decided to introduce a binding to enable pll and set it only with that. Lastly, we add support for led open drain that require the power-on-sel to set. Also, some device have only the power-on-sel set in the initval so we add also support for that. This is needed for the correct function of the switch leds. Qca8327 have a special reg in the pws regs that set it to a reduced 48pin layout. This is needed or the switch doesn't work. These are all the special configuration we find on all these devices that are from various targets. Mostly ath79, ipq806x and bcm53xx. Ansuel Smith (13): drivers: net: phy: at803x: fix resume for QCA8327 phy drivers: net: phy: at803x: add DAC amplitude fix for 8327 phy drivers: net: phy: at803x: enable prefer master for 83xx internal phy drivers: net: phy: at803x: better describe debug regs net: dsa: qca8k: add mac_power_sel support Documentation: devicetree: net: dsa: qca8k: document rgmii_1_8v bindings net: dsa: qca8k: add support for mac6_exchange, sgmii falling edge dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties net: dsa: qca8k: check rgmii also on port 6 if exchanged net: dsa: qca8k: add explicit SGMII PLL enable devicetree: net: dsa: qca8k: Document qca,sgmii-enable-pll drivers: net: dsa: qca8k: add support for pws config reg Documentation: devicetree: net: dsa: qca8k: document open drain binding .../devicetree/bindings/net/dsa/qca8k.txt | 11 ++ drivers/net/dsa/qca8k.c | 111 ++++++++++++++- drivers/net/dsa/qca8k.h | 11 ++ drivers/net/phy/at803x.c | 127 +++++++++++++++--- 4 files changed, 240 insertions(+), 20 deletions(-)